Clock Signals That Can Be Modulated - Fujitsu MB86R02 Jade-D Application Note

4 Clock Signals that can be modulated

The Hardware manual of MB86R02 'Jade-D' describes which clock signals can be modulated, some
depending on the settings in the CSEl register (which control the multiplexers SELM and SELMCCLK).
The table below serves as a reference, please refer to the latest Hardware Manual to be sure you
have the most current information.
Name Description
Reference clock
generated by oscillator or
XCLK externally, used for PLLs
and CRG module, Note 1,
2
APIXPLLCLK APIX PLL Clock
APIX core clock, used for
APIXCORECLK APIX PHY, Ashell
Main PLL Clock, used for
PLLCLK DISP, DPERI modules
Chip clock, used within
CRG module to generate
CCLK bus clocks
ARM A clock, used as
clock source for ARM
ARMACLK core and DDR2 IF
ARM B clock, used for
ARMBCLK ARM ETM module, MLB
APB clock, used for all
PACLK[x] APB peripherals
AHB (B) clock, used for
GDC,AXI, DDR2 IF, MLB
HBCLK internal
AHB (A) clock, used for
HACLK[y] MLB, SD, I2S module
AHB (A) clock, used for
the remaining AHB
HACLK[x] modules
AHB (A) clock, used for
HACLKCRG CRG
TCONBCLK TCON RSDS bit clock
DCLK Pixel dotclock
Reference clock
generated by oscillator or
XCLK externally, used for PLLs
and CRG module, Note 1,
2
Table 4-1, Clock overview list
Version 1.30
Freq. Freq.
min max
6.25 33.3
0 250
62.5 125
500 666
250 333
(SELMCCLK = 1)
0 333
(SELMCCLK = 1)
0 166
(SELMCCLK = 1)
0 41.625
(SELMCCLK = 1)
0 166
(SELMCCLK = 1)
0 83.3
(SELMCCLK = 1)
0 83.3
(SELMCCLK = 1)
0 83.3
(SELMCCLK = 1)
0 166
0 83.3
6.25 33.3
7
Modulation Stoppable
possible
no no
no yes
no yes
yes
yes
(SELM = 1)
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
(SELM = 1)
yes
yes
(SELM = 1)
no no