Motorola MPC860 PowerQUICC User Manual page 245

Bit 0 1 2
Field
Reset
R/W
Bit 16 17 18
Field
Reset
R/W
SPR
Figure 9-9. IMMU Tablewalk Control Register (MI_TWC)
Table 9-9 describes MI_TWC Þelds.
Bits Name
0Ð22 Ñ Reserved. Ignored on write. Returns 0 on read.
23Ð26 APG Access protection group. Up to 16 protection groups supported. Default for ITLB miss is 0
27 G Guarded memory attribute for entry
0 Nonguarded memory (default for ITLB miss)
1 Guarded memory
28Ð29 PS Page size level-one
00 Small (4 or 16 Kbyte. See MI_RPN[SPS]) Default for ITLB miss
01 512 Kbyte
11 8 Mbyte
10 Reserved
30 Ñ Reserved. Ignored on write. Returns 0 on read.
31 V Entry valid bit
0 Entry is not valid
1 Entry is valid. Default value on ITLB miss.
9.8.5 DMMU Tablewalk Control Register (MD_TWC)
The DMMU tablewalk control register (MD_TWC), shown in Figure 9-10, contains the
level-two pointer and access protection group of an entry to be loaded into the TLB.
MOTOROLA
3 4 5 6
0000_0000_0000_0000
19 20 21 22
Ñ
0
R/W
Table 9-9. MI_TWC Field Descriptions
Chapter 9. Memory Management Unit (MMU)
Part II. PowerPC Microprocessor Module
7 8 9 10
Ñ
R/W
23 24 25 26
APG
Ñ
R/W R/W
789
Description
11 12 13 14
27 28 29 30
G PS Ñ
Ñ Ñ 0
R/W R/W R/W
9-19
15
31
V
Ñ