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23.16 UART Mode Register (PSMR)
For UART mode, the SCC protocol-speciÞc mode register (PSMR) is called the UART
mode register. Many bits can be modiÞed while the receiver and transmitter are enabled.
Figure 23-6 shows the PSMR in UART mode.
Bit
0
1
Field
FLC
SL
Reset
R/W
Addr
Figure 23-6. Protocol-Specific Mode Register for UART (PSMR)
Table 23-9 describes PSMR UART Þelds.
Bit
Name
0
FLC
Flow control.
0 Normal operation. The GSMR and port C registers determine the mode of CTS.
1 Asynchronous ßow control. When CTS is negated, the transmitter stops at the end of the current
character. If CTS is negated past the middle of the current character, the next full character is sent
before transmission stops. When CTS is asserted again, transmission continues where it left off
and no CTS lost error is reported. Only idle characters are sent while CTS is negated.
1
SL
Stop length. Selects the number of stop bits the SCC sends. SL can be modiÞed on-the-ßy. The
receiver is always enabled for one stop bit unless the SCC UART is in synchronous mode and
PSMR[RZS] is set. Fractional stop bits are conÞgured in the DSR.
0 One stop bit.
1 Two stop bits.
2Ð3
CL
Character length. Determines the number of data bits in the character, not including optional parity or
multidrop address bits. If a character is less than 8 bits, most-signiÞcant bits are received as zeros
and are ignored when the character is sent. CL can be modiÞed on-the-ßy.
00
5 data bits
01
6 data bits
10
7 data bits
11
8 data bits
4Ð5
UM
UART mode. Selects the asynchronous channel protocol. UM can be modiÞed on-the-ßy.
00 Normal UART operation. Multidrop mode is disabled and idle-line wake-up mode is selected. The
UART receiver leaves hunt mode by receiving an idle character (all ones).
01 Manual multidrop mode. An additional address/data bit is sent with each character. Multidrop
asynchronous modes are compatible with the MC68681 DUART, MC68HC11 SCI, DSP56000
SCI, and Intel 8051 serial interface. The receiver leaves hunt mode when the address/data bit is a
one, indicating the received character is an address that all inactive processors must process.
The controller receives the address character and writes it to a new buffer. The core then
compares the written address with its own address and decides whether to ignore or process
subsequent characters.
10 Reserved.
11 Automatic multidrop mode. The CPM compares the address of an incoming address character
with UADDRx parameter RAM values; subsequent data is accepted only if a match occurs.
MOTOROLA
2
3
4
5
6
CL
UM
FRZ RZS SYN DRT
0xA08 (PSMR1), 0xA28 (PSMR2), 0xA48 (PSMR3), 0xA68 (PSMR4)
Table 23-9. PSMR UART Field Descriptions
Chapter 23. SCC UART Mode
Part V. The Communications Processor Module
7
8
9
10
11
Ñ
PEN
0
R/W
Description
12
13
14
15
RPM
TPM
23-13
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