Motorola MPC860 PowerQUICC User Manual page 680

Part V. The Communications Processor Module
Characters
Received by UART
Time
RXD Line Idle
CD
UART SCCE
CD
Events
Notes:
1. The Þrst RX event assumes Rx buffers are 6 bytes each.
2. The second IDL event occurs after an all-ones character is received.
3. The second RX event position is programmable based on the MAX_IDL value.
4. The BRKS event occurs after the Þrst break character is received.
5. The CD event must be programmed in the port C parallel I/O, not in the SCC itself.
Legend
:
A receive control character deÞned not to be stored in the Rx buffer.
Characters
Transmitted by UART
TXD Line Idle
RTS
CTS
UART SCCE
Events
Notes
:
1. TX event assumes all seven characters were put into a single buffer and TxBD[CR]=1.
2. The CTS event must be programmed in the port C parallel I/O, not in the SCC itself.
Figure 23-10. SCC UART Interrupt Event Example
SCCE bits are cleared by writing ones; writing zeros has no effect. Unmasked bits must be
cleared before the CPM clears an internal interrupt request. Figure 23-11 shows
SCCE/SCCM for UART operation.
Bit 0 1 2
Field Ñ
Reset
R/W
Addr
Figure 23-11. SCC UART Event Register (SCCE) and Mask Register (SCCM)
23-20
10 Characters
IDL RX
7 Characters
CTS
3 4 5 6
GLR GLT Ñ AB
0000_0000_0000_0000
0xA10 (SCCE1)/0xA14 (SCCM1); 0xA30 (SCCE2)/0xA34 (SCCM2)
0xA50 (SCCE3)/0xA54 (SCCM3); 0xA70 (SCCE4)/0xA74 (SCCM4)
MPC860 PowerQUICC UserÕs Manual
Line Idle
CCR IDL RX
TX CTS
7 8 9 10
IDL GRA BRKE BRKS
R/W
Break
IDL BRKS BRKE IDL CD
Line Idle
11 12 13 14
Ñ CCR BSY TX
MOTOROLA
15
RX