Motorola MPC860 PowerQUICC User Manual page 933

Table 36-16. FIR6 Parameter Packet (Continued)
Address Name
Hword 4 M Input buffer_size - 1. The minimum input buffer size is 4 (2 samples).
Hword 5 XYPTR Pointer to a structure composed of the input buffer pointer and the output buffer pointer
Hword 6 N Output buffer_size - 1. The minimum output buffer size is 8 (2 outputs).
Hword 7 Ñ Reserved
36.12 IIRÐReal C, Real X, Real Y
Using the values provided in the parameter packet, the IIR implements a basic biquad IIR
Þlter, shown in Figure 36-22, with six real coefÞcients, real input samples, and real outputs.
The input data is in a circular buffer with size (M+1) and the output data is in a circular
buffer with size (N+1). Several stages of the biquad Þlter can be cascaded by specifying an
iteration count greater than one and concatenating the Þlter coefÞcients into one vector.
C(0)
{Real}
X(n)
{Real}
36.12.1 IIR CoefÞcient, Input, and Output Buffers
The coefÞcient vector occupies six 16-bit entries in memory and C(0) is stored in the Þrst
location. C(1) is only used in the last stage of a cascaded IIR Þlter. The input sample buffer
is a circular buffer that contains (M+1) bytes. The next sample is stored in the address that
follows the previous one. The output buffer is a circular buffer that contains (N+1) bytes
and the next output is stored in the address that follows the previous one. See Table 36-17.
MOTOROLA
Part V. The Communications Processor Module
å
T
C(3)
å
T
C(2)
Figure 36-22. IIR Function
Chapter 36. Digital Signal Processing
Description
å
C(5)
å
C(4)
C(1)
Y(n)
{Real}
36-19