Motorola MPC860 PowerQUICC User Manual page 834

Part V. The Communications Processor Module
Table 31-1. SPMODE Field Descriptions (Continued)
Bits Name
8Ð11 LEN Character length in bits per character. Must be between 0011 (4 bits) and 1111 (16 bits). A value less
than 4 causes erratic behavior. If the value is not greater than a byte, every byte in memory holds LEN
valid bits. If the value is greater than a byte, every half-word holds LEN valid bits. See
Section 31.4.1.2, ÒSPI Examples with Different SPMODE[LEN] Values.Ó
12Ð15 PM Prescale modulus select. SpeciÞes the divide ratio of the prescale divider in the SPI clock generator.
BRGCLK is divided by 4 * ([PM0ÐPM3] + 1), a range from 4 to 64. The clock has a 50% duty cycle.
31.4.1.1 SPI Transfers with Different Clocking Modes
Figure 31-5 shows the SPI transfer format in which SPICLK starts toggling in the middle
of the transfer (SPMODE[CP] = 0).
SPICLK (CI = 0)
SPICLK (CI = 1)
SPIMOSI
(From Master)
SPIMISO
(From Slave)
SPISEL
NOTE: Q = UndeÞned Signal.
Figure 31-5. SPI Transfer Format with SPMODE[CP] = 0
Figure 31-6 shows the SPI transfer format in which SPICLK starts toggling at the
beginning of the transfer (SPMODE[CP] = 1).
SPICLK (CI = 0)
SPICLK (CI = 1)
SPIMOSI
(From Master)
SPIMISO
(From Slave)
SPISEL
NOTE: Q = UndeÞned Signal.
Figure 31-6. SPI Transfer Format with SPMODE[CP] = 1
31-8
msb
msb
msb
Q msb
MPC860 PowerQUICC UserÕs Manual
Description
lsb
lsb Q
lsb
lsb
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