Motorola MPC860 PowerQUICC User Manual page 604

Part V. The Communications Processor Module
Partition the frame from the beginning (the sync) to the end according to the support
needed:
¥ 8 bits (B1)ÑSCC2
¥ 1 bit (D)ÑSCC3 + strobe1
¥ 1 bitÑNo support
¥ 4 bits (B2)Ñstrobe2
¥ 4 bits (B2)ÑSMC1
¥ 1 bit (D)ÑSCC3 + strobe1
Each partition represents one SI RAM entry. Table 21-3 shows the SI RAM entries.
Table 21-3. Example SI RAM Entry Settings for an IDL Bus
Entry
Number
SWTR
1 0
2 0
3 0
4 0
5 0
6 0
Because the IDL requires the same routing for both receiving and sending, the above entries
should be written to both the Rx and Tx route RAM. Set SIMODE[CRTx] (common
receive/transmit) to instruct the TSA to use the same clock and sync for both sets of SI
RAM entries.
For examples showing register programming, see Section 21.2.5.2, ÒProgramming the IDL
Interface,Ó and Section 21.2.6.3, ÒGCI Interface (SCIT Mode) Programming Example.Ó
21.2.4 The SI Registers
The following sections describe the SI registers.
21.2.4.1 SI Global Mode Register (SIGMR)
The SI global mode register (SIGMR), shown in Figure 21-12, deÞnes the SI RAM division
modes and enables the individual TDM channels.
21-16
SSEL CSEL CNT
0000 010 0000
0001 011 0000
0000 000 0000
0010 000 0011
0000 101 0011
0001 011 0000
MPC860 PowerQUICC UserÕs Manual
SI RAM
BYT LST
1 0
0 0 1 bit SCC3 strobe1 (D)
0 0
0 0
0 0
0 1
Description
8 bits SCC2 (B1)
1 bit no support
4 bits strobe2 (B2)
4 bits SMC1 (B2)
1 bit SCC3 strobe1
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