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PITRTCLK
Clock
Figure 11-28. Periodic Interrupt Timer Block Diagram
The time-out period is calculated as follows:
Solving this equation using a 32.768-KHz external clock gives:
This gives a range from 122 ms (PITC = 0x0000) to 8 seconds (PITC = 0xFFFF).
11.11.1 Periodic Interrupt Status and Control Register (PISCR)
The read/write periodic interrupt status and control register (PISCR) contains the interrupt
request level and status bits. It also controls the 16 bits to be loaded in a modulus counter.
Note that PISCR is a keyed register. It must be unlocked in PISCRK before it can be
written.
Bit
0
1
Field
Reset
R/W
Addr
Figure 11-29. Periodic Interrupt Status and Control Register (PISCR)
MOTOROLA
PTE
Clock
16-Bit
Disable
Modulus Counter
FRZ
PITC 1
PIT
=
-------------------------
period
F
pitrtclk
PITperiod
2
3
4
5
6
PIRQ
0000_0000_0000_0000
(IMMR & 0xFFFF0000) + 0x240
Chapter 11. System Interface Unit
PITC
PS
PIE
+
PITC 1
+
=
----------------------------------------------------------- -
æ
ö 4
ExternalClock
¸
------------------------------------------
è
ø
o
o
1
or
128
PITC 1
+
=
-------------------------
8192
7
8
9
10
PS
R/W
Part III. Configuration
PIT
Interrupt
11
12
13
14
Ñ
PIE PITF PTE
15
11-31
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