Motorola MPC860 PowerQUICC User Manual page 419

In this conÞguration, PORESET, HRESET, and SRESET should be pulled up to KAPWR,
in order to keep them from being unintentionally sampled as asserted and causing an
unintended exit from power-down mode.
This scheme is illustrated in Figure 15-14.
MPC860
Figure 15-14. Software-initiated Power-down Configuration
Switches for VDDH, VDDL, and VDDSYN are shown separately; however, if they are
actually supplied from the same source, there would in actuality be only a single switch.
When PLPRCR[TEXPS] is cleared, TEXP is deasserted and the power is shut down.
PLPRCR[TEXPS], is asserted by the MPC860 when the real-time clock or timebase time
value matches the value programmed in its associated alarm register or when the periodic
interrupt timer or decrementer decrements their value to zero, or when the HRESET signal
is externally asserted.
15.5.7.2 Maintaining the Real-Time Clock (RTC) During Shutdown or
Power Failure
The power-down conÞguration can be used simply to maintain integrity of the real-time
clock (RTC) if a power shutdown or power failure should occur. The backup KAPWR
source is used to maintain the RTC. In this conÞguration, no provision is made for
automatic wake-up from power-down mode. Instead, it is assumed that the appropriate reset
MOTOROLA
VDDSYN
VDDH
VDDL
KAPWR
PORESET
HRESET
SRESET
TEXP Switch
Logic
Chapter 15. Clocks and Power Control
Part IV. Hardware Interface
SW1 Main Power
Supply
3.3V
SW2
SW3
3.3V
Backup
Power
Supply
15-25