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Part II. PowerPC Microprocessor Module
Functionality
Address
If address translation is disabled (MSR[IR] = 0 for instruction accesses or MSR[DR] = 0 for data
translation
accesses), the EA is treated as the physical address and is passed directly to the memory
subsystem. Otherwise, the EA is translated by using the MMUÕs TLB mechanism. Instructions are
not fetched from no-execute or guarded memory and data accesses are not executed speculatively
to or from the guarded memory. The features of the MMU hardware are as follows:
¥ 32-entry fully associative ITLB
¥ 32-entry fully associative DTLB
¥ Supports up to 16 virtual address spaces
¥ Supports 16 access protection groups
¥ Supports fast software table search mechanism
The MPC860 MMU is described in detail in Chapter 9, ÒMemory Management Unit (MMU).Ó
Reference and
No reference bit is supported by the MPC860. However, the change bit is supported by using the
change bits
data TLB error exception mechanism when writing to an unmodiÞed page.
Memory
Two protection modes are supported by the MPC860:
protection
¥ Domain manager mode
¥ PowerPC mode
See Chapter 9, ÒMemory Management Unit (MMU).Ó
4-18
Table 4-5. OEA-Level Features (Continued)
MPC860 PowerQUICC UserÕs Manual
Description
MOTOROLA
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