Motorola MPC860 PowerQUICC User Manual page 930

Part V. The Communications Processor Module
Table 36-13. FIR5 Coefficient, Input, and Output Buffers (Continued)
real{C(k-1)}
36.11.4.2 FIR5 Function Descriptor
The FIR5 function descriptor is shown in Figure 36-18.
0 1
Offset + 0 S Ñ
Offset + 0x2
Offset + 0x4
Offset + 0x6
Offset + 0x8
Offset + 0xA
Offset + 0xC
Offset + 0xE
The status and control bits (at offset 0x00) are described in Table 36-2. The FIR5 parameter
packet consists of seven 16-bit entries and is described in Table 36-14.
Address Name
Hword 1 I Number of iterations
Hword 2 K Number_of_taps - 1
Hword 3 CBASE Filter coefÞcient vector base address
Hword 4 M Input buffer_size - 1. The minimum input buffer size is 8 (2 samples).
Hword 5 XYPTR Pointer to a structure composed of the input buffer pointer and the output buffer pointer
Hword 6 N Output buffer size - 1. The minimum output buffer size for FD[X] = 1 is 8 (2 outputs). The
minimum output buffer size for FD[X] = 0 is 4 (2 outputs).
Hword 7 Ñ Reserved
36.11.4.3 FIR5 Applications
The FIR5 is used for fractionally spaced equalizers. The partial FD shown in Figure 36-19
can be used to implement a fractionally spaced equalizer.
36-16
real{x(n-2)}
imaginary{x(n-1)}
real{x(n-1)}
imaginary{x(n)}
real{x(n)}
2 3 4 5
W I X IALL
Figure 36-18. FIR5 Function Descriptor
Table 36-14. FIR5 Parameter Packet
MPC860 PowerQUICC UserÕs Manual
real{Y(n-2)}
imaginary{Y(n-1)}
real{Y(n-1)}
imaginary{Y(n)}
real{Y(n)}
6 7 8 9 10
INDEX PC Ñ Ñ
I
K
CBASE
M
XYPTR
N
Ñ
Description
Y(n)
11 12 13 14 15
00101
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