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Chapter 15
Clocks and Power Control
150
150
The MPC860 clock system provides many different clocking options for all on-chip and
external devices. For its clock sources, the MPC860 contains phase-locked loop and crystal
oscillator support circuitry. The phase-locked loop circuitry can be used to provide a
high-frequency system clock from a low-frequency external source. Also, to enable ßexible
power control, the MPC860 provides frequency dividers and a variety of low-power mode
options.
The MPC860 allows a system to optimize power utilization by providing performance
on-demand. This is implemented through a variety of programmable power-saving modes
with automatic wake-up features.
Figure 15-1 illustrates internal clock source and distribution that includes the system
phase-locked loop (SPLL), clock dividers, drivers, and crystal oscillator.
15.1 Features
The main features of the MPC860 clocks and power control system are as follows:
¥ Contains system PLL (SPLL)
¥ Supports crystal oscillator circuits
¥ Clock dividers are provided for low-power modes and internal clocks
¥ Contains Þve major power-saving modes
Ñ Normal (high and low)
Ñ Doze (high and low)
Ñ Sleep
Ñ Deep sleep
Ñ Power down
MOTOROLA
Chapter 15. Clocks and Power Control
15-1
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