Motorola MPC860 PowerQUICC User Manual page 628

Part V. The Communications Processor Module
The BRG provides a divide-by-16 option (BRGCn[DIV16]) and a 12-bit prescaler
(BRGCn[CD]) to divide the source clock frequency. The combined source-clock divide
factor can be changed on-the-ßy; however, two changes should not occur within a time
equal to two source clock periods.
The prescaler output is sent internally to the bank of clocks and can also be output
externally on BRGOn through either the port A or port B parallel I/O. If the BRG divides
the clock by an even value, the transitions of BRGOn always occur on the falling edge of
the source clock. If the divide factor is an odd value, the transitions alternate between the
falling and rising edges of the source clock. Additionally, the output of the BRG can be sent
to the autobaud control block.
21.4.1 Baud Rate Generator ConÞguration Registers (BRGCn)
Each baud rate generator conÞguration register (BRGC), shown in Figure 21-30, is cleared
at reset. A reset disables the BRG and drives the BRGO output clock high. The BRGC can
be written at any time with no need to disable the SCCs or external devices that are
connected to BRGO. ConÞguration changes occur at the end of the next BRG clock cycle
(no spikes occur on the BRGO output clock). BRGC can be changed on-the-ßy; however,
two changes should not occur within a time equal to two source clock periods.
Bit 0 1
Field
Reset
R/W
Addr
Bit 16 17
Field EXTC ATB
Reset
R/W
Addr
Figure 21-30. Baud Rate Generator Configuration Registers (BRGCn)
Table 21-13 describes the BRGCn Þelds.
Bits Name
0Ð13 Ñ Reserved, should be cleared.
14 RST Reset BRG. Performs a software reset of the BRG identical to that of an external reset. A reset
disables the BRG and drives BRGO high. This is externally visible only if BRGO is connected to the
corresponding parallel I/O pin.
0 Enable the BRG.
1 Reset the BRG (software reset).
21-40
2 3 4 5
0x9F0 (BRGC1), 0x9F4 (BRGC2), 0x9F8 (BRGC3), 0x9FC (BRGC4)
18 19 20 21 22
0x9F2 (BRGC1), 0x9F6 (BRGC2), 0x9FA (BRGC3), 0x9FE (BRGC4)
Table 21-13. BRGCn Field Descriptions
MPC860 PowerQUICC UserÕs Manual
6 7 8 9 10
Ñ
0
R/W
23 24 25 26
CD
0
R/W
Description
11 12 13 14
RST EN
27 28 29 30
DIV16
MOTOROLA
15
31