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Part VI. Debug and Test
¥ A simple method is provided for memory dump and load via the data register of the
development port that is accessed with mtspr and mfspr.
¥ The processor enters privileged state (MSR[PR] = 0) in debug mode, allowing
execution of any instruction and access to any memory location.
¥ An OR signal of all interrupt cause register (ICR) bits enables the development port
to detect pending events while already in debug mode. For example, the
development port can detect a debug mode access to a nonexisting memory space.
¥ Caches and MMUs are frozen in debug mode. All accesses made during debug mode
will be to the memory. Cache contents can only be accessed via SPRs.
37.3.1.1 Debug Mode Enable vs. Debug Mode Disable
For protection purposes, there are two working modes, debug mode enable and debug mode
disable, which are selected once at reset. Debug mode is enabled by asserting DSCK during
reset. The state of this pin is sampled three clocks before the negation of SRESET. If DSCK
is sampled negated, debug mode is disabled until a subsequent reset when DSCK is
asserted. When debug mode is disabled, the internal watchpoint/breakpoint hardware
remains operational and can be used for debugging by a software monitor program.
Figure 37-7 is a timing diagram for the enabling debug mode.
CLKOUT
0
SRESET
DSCK
DSCK asserts high while SRESET asserted to enable debug mode operation.
DSCK asserts high after SRESET negation to enter debug mode immediately (without fetching reset vector).
Figure 37-7. Debug Mode Reset Configuration Timing Diagram
Note that because SRESET negation time depends on an external pull-up resistor, any
reference to SRESET negation time in this chapter refers to the time the MPC860 releases
SRESET. If SRESET rise time is long because of a large resistor, the setup time for debug
port signals should be adjusted accordingly.
When debug mode is disabled, all development support registers are accessible when
MSR[PR] = 0 and can be used by monitor debugger software. However, the processor never
enters debug mode and the ICR and DER are used only for asserting and negating the freeze
signal. For more information on the software monitor debugger support, see Section 37.4,
ÒSoftware Monitor Debugger Support.Ó All development support registers accessible only
when the core is in debug mode; therefore, the development system has full control of the
coreÕs development support features. For more information, see Table 37-15. If debug
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MOTOROLA
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