Motorola MPC860 PowerQUICC User Manual page 901

Bit 0 1
Field Ñ
Reset
R/W
Addr
Table 34-18 describes PDDAT bits.
Bits Name
0Ð2 Ñ Reserved
3Ð15 Dn Contains the data on the corresponding signal.
34.5.1.2 Port D Data Direction Register (PDDIR)
The port D data direction register (PDDIR) provides bits for specifying whether port D
signals are inputs or outputs when functioning as general-purpose I/O.
Bit 0 1 2
Field Ñ
Reset
R/W
Addr
Figure 34-17. Port D Data Direction Register (PDDIR)
Table 34-19 describes PDDIR bits.
Bits Name
0Ð2 Ñ Reserved and should be cleared.
3Ð15 DRn Port D data direction. ConÞgures port D signals as inputs or outputs when functioning as
general-purpose I/O.
0 The corresponding signal is an input.
1 The corresponding signal is an output.
34.5.1.3 Port D Pin Assignment Register (PDPAR)
The port D pin assignment register (PDPAR) conÞgures signals as general-purpose I/O or
dedicated for use with a peripheral.
MOTOROLA
2 3 4 5 6
Figure 34-16. Port D Data Register (PDDAT)
Table 34-18. PDDAT Bit Descriptions
3 4 5 6
DR3 DR4 DR5 DR6 DR7 DR8 DR9 DR10 DR11 DR12 DR13 DR14 DR15
0000_0000_0000_0000
Table 34-19. PDDIR Bit Descriptions
Chapter 34. Parallel I/O Ports
Part V. The Communications Processor Module
7 8 9 10
D3ÐD15
UndeÞned
R/W
0x976
Description
7 8 9 10 11
R/W
0x970
Description
11 12 13 14 15
12 13 14 15
34-19