Motorola MPC860 PowerQUICC User Manual page 461

System Clock
CLKOUT
GCLK1_50
GCLK2_50
CS
GPL1
GPL2
Clock Phase
Figure 16-37. UPM Signals Timing Example Two (Division Factor = 2, EBDF = 01)
16.6.4 The RAM Array
The RAM array for each UPM is 64 locations deep and 32 bits wide, as shown in
Figure 16-38. The signals at the bottom of Figure 16-38 are UPM outputs. The selected CS
is for the bank that matches the current address. The selected BS is for the byte lanes read
or written by the access.
GCLK1_50
GCLK2_50
CS Signal
Selected Bank
Figure 16-38. RAM Array and Signal Generation
MOTOROLA
CST4 CST1 CST2
G1T4
G2T4
1 2 3
RAM Word 1
32-Bits Wide
RAM Array
Signals Timing Generator
CS
Selector
CS[0Ð7] GPL0 GPL1 GPL2 GPL3 GPL4 GPL5
Chapter 16. Memory Controller
CST3 CST4 CST1
G1T3 G1T4
G2T3 G2T4
4 1 2
RAM Word 2
BS
BS Signal
Selector
BS[0Ð3]
Part IV. Hardware Interface
CST2 CST3
G1T4 G1T3
G1T4 G2T3
3 4
64 RAM
Words Deep
TSIZ, PS, A[30Ð31]
16-35