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Part IV. Hardware Interface
16.2 Basic Architecture
The memory controller consists of three basic machines
¥ General-purpose chip-select machine (GPCM)
¥ User-programmable machine A (UPMA)
¥ User-programmable machine B (UPMB)
Each bank can be assigned to any one of these machines via the BRx[MS] bits as shown in
Figure 16-2. Address decode is performed by the comparison of (A[0Ð16] bit-wise and
ORx[AM]) with BRx[BA]. If an address match occurs in multiple banks, the lowest
numbered bank has priority. When a memory address matches BRx[BA], the corresponding
machine takes ownership of the external signals that control access until the cycle ends.
Bank 0
Bank 1
Bank 2
Bank 3
Bank 4
Bank 5
Bank 6
Bank 7
Figure 16-2. Memory Controller Machine Selection
The GPCM provides a glueless interface to EPROM, SRAM, ßash EPROM, and other
peripherals. GPCM signals are available on CS[0Ð7]. CS0 lets the CPU access the boot
EPROM from reset. Each chip-select allows up to 30 wait states.
Some features are common to all eight memory banks.
¥ The block size of each memory bank can vary between 32 Kbytes and 256 Mbytes
for a full 4 Gbytes of the address space.
¥ Parity can be generated and checked for any memory bank. The memory controller
has four parity signals (DP[0Ð3]), one for each data byte lane on the MPC860 system
bus. The parity on the bus is checked only if the memory bank accessed in the current
transaction has parity enabled. Parity checking/generation can be enabled for a
16-4
BR0[MS]
BR1[MS]
BR2[MS]
BR3[MS]
BR4[MS]
BR5[MS]
BR6[MS]
BR7[MS]
MPC860 PowerQUICC UserÕs Manual
UPMA
UPMB
GPCM
MOTOROLA
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