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Figure
Number
34-6
Block Diagram for PA14 (True for all Open-Drain Port Signals)..................... 34-7
34-7
Port B Open-Drain Register (PBODR).............................................................. 34-9
34-8
Port B Data Register (PBDAT)........................................................................ 34-10
34-9
Port B Data Direction Register (PBDIR)......................................................... 34-11
34-10
Port B Pin Assignment Register (PBPAR) ...................................................... 34-11
34-11
Port C Data Register (PCDAT)........................................................................ 34-15
34-12
Port C Data Direction Register (PCDIR)......................................................... 34-15
34-13
Port C Pin Assignment Register (PCPAR) ...................................................... 34-16
34-14
Port C Special Options Register (PCSO)......................................................... 34-16
34-15
Port C Interrupt Control Register (PCINT) ..................................................... 34-17
34-16
Port D Data Register (PDDAT) ....................................................................... 34-19
34-17
Port D Data Direction Register (PDDIR) ........................................................ 34-19
34-18
Port D Pin Assignment Register (PDPAR)...................................................... 34-20
35-1
MPC860 Interrupt Structure .............................................................................. 35-2
35-2
Interrupt Request Masking................................................................................. 35-5
35-3
CPM Interrupt Configuration Register (CICR) ................................................. 35-7
35-4
CPM Interrupt Pending/Mask/In-Service Registers (CIPR/CIMR/CISR) ........ 35-8
35-5
CPM Interrupt Vector Register (CIVR)........................................................... 35-10
36-1
DSP Functionality Implementation.................................................................... 36-2
36-2
DSP Function Descriptor (FD) Chain Structure ................................................ 36-3
36-3
Function Descriptor (FD) Structure ................................................................... 36-3
36-4
Real Number Representation ............................................................................. 36-4
36-6
Circular Buffer ................................................................................................... 36-5
36-5
Complex Number Representation...................................................................... 36-5
36-7
DSP Event/Mask Registers (SDSR/SDMR)...................................................... 36-7
36-8
FIR1 Function .................................................................................................... 36-8
36-9
FIR1 Function Descriptor .................................................................................. 36-9
36-11
FIR2 Function .................................................................................................. 36-10
36-10
FIR1 Decimation Example .............................................................................. 36-10
36-12
FIR2 Function Descriptor ................................................................................ 36-11
36-13
FIR2 Filter Example ........................................................................................ 36-12
36-14
FIR3 Function .................................................................................................. 36-13
36-15
FIR3 Function Descriptor ................................................................................ 36-14
36-16
FIR3 Echo Cancellation Example.................................................................... 36-14
36-17
FIR5 Function .................................................................................................. 36-15
36-18
FIR5 Function Descriptor ................................................................................ 36-16
36-20
FIR6 Function .................................................................................................. 36-17
36-19
FIR5 Fractionally Spaced Equalizer Example................................................. 36-17
36-21
FIR6 Function Descriptor ................................................................................ 36-18
36-22
IIR Function ..................................................................................................... 36-19
36-23
IIR Function Descriptor ................................................................................... 36-20
36-24
MOD Function ................................................................................................. 36-21
36-25
MOD Function Descriptor ............................................................................... 36-22
xlviii
ILLUSTRATIONS
Title
MPC860 PowerQUICC UserÕs Manual
Page
Number
MOTOROLA
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