Motorola MPC860 PowerQUICC User Manual page 170

Part II. PowerPC Microprocessor Module
6.2.5.1 Processor Control Instructions
In addition to the move to condition register instructions speciÞed by the UISA, the VEA
deÞnes the Move from Time Base (mftb) instruction for reading the contents of the time
base register. The mftb is a user-level instruction, it is shown in Table 6-17.
SimpliÞed mnemonics are provided for the mftb instruction so it can be coded with the
TBR name as part of the mnemonic rather than requiring it to be coded as an operand. The
mftb instruction serves as both a basic and simpliÞed mnemonic. Assemblers recognize an
mftb mnemonic with two operands as the basic form, and an mftb mnemonic with one
operand as the simpliÞed form. SimpliÞed mnemonics are also provided for Move from
Time Base Upper (mftbu), which is a variant of the mftb instruction rather than of mfspr.
The MPC860 ignores the extended opcode differences between mftb and mfspr by
ignoring bit 25 of both instructions and treating them both identically. For more information
refer to Appendix F, ÒSimpliÞed Mnemonics,Ó in The Programming Environments Manual.
Move from Time Base
6.2.5.2 Memory Synchronization InstructionsÑVEA
Memory synchronization instructions control the order in which memory operations are
completed with respect to asynchronous events, and the order in which memory operations
are seen by other processors or memory access mechanisms. See Chapter 8, ÒInstruction
and Data Caches,Ó for additional information about these instructions and about related
aspects of memory synchronization.
Table 6-18 lists the VEA memory synchronization instructions for the MPC860.
Table 6-18. Memory Synchronization InstructionsÑVEA
Name Mnemonic Syntax
Enforce In-Order eieio
Execution of I/O
Instruction isync
Synchronize
6.2.5.2.1 eieio Behavior
The purpose of eieio is to prevent loads and stores from executing speculatively when
appropriate, This might be desirable for a FIFO, where performing a read or write changes
the FIFO's data. This should not be done unless it is certain that the instruction will be
completed and not cancelled.
The same function as eieio can be accomplished by deÞning a memory space as having the
guarded attribute in the MMU, in which case, the eieio instruction is redundant.
6-20
Table 6-17. Move from Time Base Instruction
Name
Ñ During execution, the LSU waits for previous accesses to terminate before
beginning accesses associated with load/store instructions after an eieio.
Ñ The isync instruction waits for all previous instructions to complete and
discards any prefetched instructions, causing subsequent instructions to be
refetched from memory.
MPC860 PowerQUICC UserÕs Manual
Mnemonic Syntax
mftb rD, TBR
MPC860 Notes
MOTOROLA