Motorola MPC860 PowerQUICC User Manual page 876

Part V. The Communications Processor Module
33.7.2 Pulsed Handshake Mode
The pulsed handshake mode, shown in Figure 33-12, supports a Centronics-compatible
interface.
Write from Handshake
Control Logic (DIR = OUT)
CP/Core
In Use
Tx Data
STB
CP/Core
In Use
Rx Data
ACK
¥ When sending, the PIP generates STB when data is ready in the PIP output latch and
the previous transfer is acknowledged. The setup time and the pulse width of STB
are programmable.
¥ When receiving, the PIP uses STB to latch input data and ACK to acknowledge the
transfer. The timing of ACK is also programmable.
The core conÞgures the PIP to implement a Centronics protocol by programming the PIP
conÞguration (PIPC) register. When the PIP is under CP control, timing attributes are set in
PTPR. Transmit and receive errors are reported through BDs. For information about
supporting a Centronics interface, see Section 33.9, ÒImplementing Centronics.Ó
33-16
Read from CP
Latch
Byte A
PIP Transmit
PIP Receive
Figure 33-12. Pulsed Handshake Full Cycle
MPC860 PowerQUICC UserÕs Manual
Peripheral Bus
Latch
I/O
Byte B
Byte A
Write from CP
DIR = Output
Pin
Byte B
MOTOROLA