Table of Contents
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Table
Number
16-18
AMA/AMB Definition for DRAM Interface ...................................................... 16-45
16-19
UPMA Register Settings ..................................................................................... 16-60
16-20
UPMB Register Settings...................................................................................... 16-71
17-1
PCMCIA Cycle Control Cycles ............................................................................ 17-3
17-2
PCMCIA Input Port Signals.................................................................................. 17-4
17-3
PCMCIA Output Port Signals ............................................................................... 17-5
17-4
Other PCMCIA Signals......................................................................................... 17-5
17-5
Host Programming for Memory Cards.................................................................. 17-6
17-6
Host Programming For I/O Cards ......................................................................... 17-6
17-7
PCMCIA Registers................................................................................................ 17-8
17-8
PIPR Field Descriptions ........................................................................................ 17-8
17-9
PSCR Field Descriptions....................................................................................... 17-9
17-10
PER Field Descriptions ....................................................................................... 17-11
17-11
PGCRx Field Descriptions .................................................................................. 17-12
17-12
PBR Field Descriptions ....................................................................................... 17-13
17-13
POR Field Descriptions....................................................................................... 17-14
18-1
TGCR Field Descriptions ...................................................................................... 18-8
18-2
TMR1ÐTMR4 Field Descriptions ......................................................................... 18-9
18-3
TER Field Descriptions ....................................................................................... 18-11
19-1
Peripheral Prioritization......................................................................................... 19-3
19-2
CP Microcode Revision Number........................................................................... 19-4
19-3
RCCR Field Descriptions ...................................................................................... 19-5
19-4
CPCR Field Descriptions ...................................................................................... 19-6
19-5
CP Command Opcodes.......................................................................................... 19-7
19-6
CP Commands ....................................................................................................... 19-8
19-7
General BD Structure .......................................................................................... 19-11
19-8
Parameter RAM Memory Map............................................................................ 19-11
19-9
RISC Timer Table Parameter RAM Memory Map ............................................. 19-13
19-10
TM_CMD Field Descriptions.............................................................................. 19-14
19-11
PWM Channel Pin Assignments ......................................................................... 19-16
20-1
U-Bus Arbitration IDs ........................................................................................... 20-2
20-2
SDCR Bit Settings................................................................................................. 20-4
20-3
SDSR Field Descriptions....................................................................................... 20-5
20-4
IDMA Parameter RAM Memory Map .................................................................. 20-6
20-5
DCMR Field Descriptions..................................................................................... 20-8
20-6
IDSR1/IDSR2 Field Descriptions ......................................................................... 20-8
20-7
IDMA BD Status and Control Bits...................................................................... 20-10
20-8
SFCR and DFCR Field Descriptions.................................................................. 20-11
20-9
Single-Buffer Mode IDMA1 Parameter RAM Map ........................................... 20-18
20-10
DCMR Field Descriptions (Single-Buffer Mode)............................................... 20-19
21-1
TSA Signals........................................................................................................... 21-7
21-2
SIRAM Field Descriptions .................................................................................. 21-14
21-3
Example SI RAM Entry Settings for an IDL Bus ............................................... 21-16
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