Motorola MPC860 PowerQUICC User Manual page 103

Name Type
KR/RETRY Bidirectional
IRQ4 Three-state
SPKROUT
CR Input
IRQ3
D[0Ð31] Bidirectional
Three-state
DP0 Bidirectional
IRQ3 Three-state
DP1 Bidirectional
IRQ4 Three-state
DP2 Bidirectional
IRQ5 Three-state
MOTOROLA
Table 3-1. Signal Descriptions (Continued)
Kill ReservationÑThis input is used as a part of the storage reservation protocol,
when the MPC860 initiated a transaction as the result of a stwcx. instruction.
RetryÑInput is used by the slave device to indicate that it cannot accept the
transaction. The MPC860 must relinquish bus ownership and reinitiate the
transaction after winning in the bus arbitration.
Interrupt Request 4ÑOne of eight external inputs that can request (by means of the
internal interrupt controller) a service routine from the core. Note that the interrupt
request signal that is sent to the interrupt controller is the logical AND of this line (if
deÞned as IRQ4) and DP1/IRQ4 (if deÞned as IRQ4).
SPKROUTÑDigital audio wave form output to be driven to the system speaker.
Cancel ReservationÑThis input is used as a part of the storage reservation protocol.
Interrupt Request 3ÑOne of eight external inputs that can request (by means of the
internal interrupt controller) a service routine from the core. Note that the interrupt
request signal sent to the interrupt controller is the logical AND of CR/IRQ3 (if
deÞned as IRQ3) and DP0/IRQ3 if deÞned as IRQ3.
Data BusÑThis bidirectional three-state bus provides the general-purpose data path
between the MPC860 and all other devices. The 32-bit data path can be dynamically
sized to support 8-, 16-, or 32-bit transfers. D0 is the msb of the data bus.
Data Parity 0ÑThis line provides parity generation and checking for D[0Ð7] for
transfers to a slave device initiated by the MPC860. The parity function can be
deÞned independently for each one of the addressed memory banks (if controlled by
the memory controller) and for the rest of the slaves sitting on the external bus. Parity
generation and checking is not supported for external masters.
Interrupt Request 3ÑOne of eight external inputs that can request (by means of the
internal interrupt controller) a service routine from the core. Note that the interrupt
request signal sent to the interrupt controller is the logical AND of DP0/IRQ3 (if
deÞned as IRQ3) and CR/IRQ3 (if deÞned as IRQ3).
Data Parity 1ÑThis line provides parity generation and checking for D[8Ð15] for
transfers to a slave device initiated by the MPC860. The parity function can be
deÞned independently for each one of the addressed memory banks (if controlled by
the memory controller) and for the rest of the slaves on the external bus. Parity
generation and checking is not supported for external masters.
Interrupt Request 4ÑOne of eight external inputs that can request (by means of the
internal interrupt controller) a service routine from the core. Note that the interrupt
request signal sent to the interrupt controller is the logical AND of this line (if deÞned
as IRQ4) and KR/IRQ4/SPKROUT (if deÞned as IRQ4).
Data Parity 2ÑThis line provides parity generation and checking for D[16Ð23] for
transfers to a slave device initiated by the MPC860. The parity function can be
deÞned independently for each one of the addressed memory banks (if controlled by
the memory controller) and for the rest of the slaves on the external bus. Parity
generation and checking is not supported for external masters.
Interrupt Request 5ÑOne of eight external inputs that can request (by means of the
internal interrupt controller) a service routine from the core.
Chapter 3. Hardware Interface Overview
Description
Part I. Overview
3-5