Motorola MPC860 PowerQUICC User Manual page 482

Part IV. Hardware Interface
CLKOUT
GCLK1
A[0Ð31]
BURST
TS
R/W
D[0Ð31]
TA
CS1 (RAS)
BS[0Ð3] (CAS[0Ð3])
BADDR[28Ð29]
GPL5
cst4 Bit 0
cst1 Bit 1
cst2 Bit 2
cst3 Bit 3
bst4 Bit 4
bst1 Bit 5
bst2 Bit 6
bst3 Bit 7
g0l0 Bit 8
¥ ¥
¥ ¥
¥ ¥
g5t4 Bit 20
g5t3 Bit 21
Ð Bit 22
Ð Bit 23
loop Bit 24
exen Bit 25
amx0 Bit 26
amx1 Bit 27
na Bit 28
uta Bit 29
todt Bit 30
last Bit 31
Figure 16-50. Synchronous External Master: Burst Read Access to Page Mode
16-56
L/4
0 0 0
0 0 0
0 0 0
0 0 0
1 1 0
1 0 0
1 0 1
1 0 1
0 1 1
0 1 1
0 0 0
0 0 1
0 0 0
0 0 0
0 0 1
1 0 1
0 0 0
0 0 0
RBS RBS+1 RBS+2 RBS+3 RBS+4 RBS+5 RBS+6 RBS+7 RBS+8
DRAM
MPC860 PowerQUICC UserÕs Manual
L/4 + 1 Mod 4 L/4 + 2 Mod 4
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
1 0 1 0
0 0 0 0
0 1 0 1
0 1 0 1
1 1 1 1
1 1 1 1
0 0 0 0
0 1 0 1
0 0 0 0
0 0 0 0
0 1 0 1
0 1 0 1
0 0 0 0
0 0 0 0
L/4 + 3 Mod 4
0 0
0 0
0 1
0 1
1 0
0 0
0 1
0 1
1 1
1 1
0 0
0 0
0 X
0 X
0 X
0 1
0 1
0 1
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