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4.1.1 Levels of the PowerPC Architecture
The PowerPC architecture is deÞned in three levels that correspond to three programming
environments, roughly described from the most general, user-level instruction set
environment, to the more speciÞc, operating environment.
This layering of the architecture provides ßexibility, allowing degrees of software
compatibility across a wide range of implementations. For example, an implementation
such as an embedded controller may support the user instruction set, whereas it may be
impractical for it to adhere to the memory management, exception, and cache models.
The three levels of the PowerPC architecture are deÞned as follows:
¥ PowerPC user instruction set architecture (UISA)ÑThe UISA deÞnes the level of
the architecture to which user-level (referred to as problem state in the architecture
speciÞcation) software should conform. The UISA deÞnes the base user-level
instruction set, user-level registers, data types, the exception model as seen by user
programs, and the memory and programming models.
¥ PowerPC virtual environment architecture (VEA)ÑThe VEA deÞnes additional
user-level functionality that falls outside typical user-level software requirements.
The VEA describes the memory model for an environment in which multiple
devices can access memory, deÞnes aspects of the cache model, deÞnes cache
control instructions, and deÞnes the time base facility from a user-level perspective.
Implementations that conform to the PowerPC VEA also adhere to the UISA, but
may not necessarily adhere to the OEA.
¥ PowerPC operating environment architecture (OEA)ÑThe OEA deÞnes
supervisor-level (referred to as privileged state in the architecture speciÞcation)
resources typically required by an operating system. The OEA deÞnes the PowerPC
memory management model, supervisor-level registers, synchronization
requirements, and the exception model. The OEA also deÞnes the time base feature
from a supervisor-level perspective.
Implementations that conform to the PowerPC OEA also conform to the PowerPC
UISA and VEA.
The MPC860 adheres to the OEA deÞnition of the exception model and provides a
subset of the memory management model. It includes OEA-deÞned registers and
instructions for conÞguration and exception handling.
Implementations that adhere to the VEA level are guaranteed to adhere to the UISA level;
likewise, implementations that conform to the OEA level are also guaranteed to conform to
the UISA and the VEA levels. For a more detailed discussion of the characteristics of the
PowerPC architecture, see the Programming Environments Manual.
For details regarding the MPC860 as a PowerPC implementation, see Section 4.6, ÒThe
MPC860 and the PowerPC Architecture.Ó
MOTOROLA
Chapter 4. The PowerPC Core
Part II. PowerPC Microprocessor Module
4-3
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