Motorola MPC860 PowerQUICC User Manual page 600

Part V. The Communications Processor Module
Initial State
1)
The TSA uses the first part of
the RAM, and the shadow is
the second part of the RAM.
CSRxn = 0
CSRRa=0
CSRTa=0
CSRRb=0
CSRTb=0
Programming
2)
The user programs the
shadow RAM for the new
Rx and Tx route and sets
CSRxn.
CSRRa=1
CSRTa=1
CSRRb=1
CSRTb=1
Swap
3)
The SI swaps between
the shadow and the
current-route RAMs
and resets CSRxn.
CSRRa=0
CSRTa=0
CSRRb=0
CSRTb=0
Figure 21-7. SI RAM Dynamic Changes with TDMa and TDMb
The entire SI RAM is always readable, but only the shadow RAM is safe to write. The SI
status register (SISTR) can be read to determine which part of the RAM is the current-route
RAM. The SI RAM pointer (SIRP) register can be used to determine which SI RAM entry
is active. In addition, by externally connecting a strobe to an interrupt signal, an individual
SI RAM entry can generate an interrupt.
21-12
0
RAM Address:
16 RXa
Route
L1RCLKa
Framing Signals: L1RSYNCa
256
RAM Address:
16 TXa
Route
L1TCLKa
Framing Signals: L1TSYNCa
RAM Address: 0
16 RXa
Route
L1RCLKa
Framing Signals:
L1RSYNCa
RAM Address: 256
16 TXa
Route
L1TCLKa
Framing Signals: L1TSYNCa
RAM Address: 0
16 RXa
Shadow
Framing Signals:
RAM Address: 256
16 TXa
Shadow
Framing Signals:
MPC860 PowerQUICC UserÕs Manual
63 64 127 128
16 RXb
16 RXa
Shadow Route
L1RCLKb
L1RSYNCb
319 320 383 384
16 TXb
16 TXa
Shadow Route
L1TCLKb
L1TSYNCb
63 64 127 128
16 RXb
16 RXa
Shadow Route
L1RCLKb
L1RSYNCb
319 320 383 384
16 TXb
16 TXa
Shadow Route
L1TCLKb
L1TSYNCb
63 64 127 128
16 RXb
16 RXa
Route Shadow
L1RCLKa
L1RSYNCa
319 320 383 384
16 TXb
16 TXa
Route Shadow
L1TCLKa
L1TSYNCa
191 192 255
16 RXb
Shadow
447 448 511
16 TXb
Shadow
191 192 255
16 RXb
Shadow
447 448 511
16 TXb
Shadow
191 192 255
16 RXb
Route
L1RCLKb
L1RSYNCb
447 448 511
16 TXb
Route
L1TCLKb
L1TSYNCb
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