Processor Version Register - Motorola MPC860 PowerQUICC User Manual

Part II. PowerPC Microprocessor Module
Table 5-8. MSR Field Descriptions (Continued)
Bit(s) Name
1
21 SE Single-step trace enable (Optional)
0 The processor executes instructions normally.
1 A single-step trace exception is generated when the next instruction executes successfully.
Note: If the function is not implemented, SE is treated as reserved.
1
22 BE Branch trace enable (Optional)
0 The processor executes branch instructions normally.
1 The processor generates a branch trace exception after completing the execution of a branch
instruction, regardless of whether the branch was taken.
Note: If the function is not implemented, this bit is treated as reserved.
23Ð24 Ñ Reserved
25 IP Exception preÞx. The setting of IP speciÞes whether an exception vector offset is prepended with Fs
or 0s. In the following description, nnnnn is the offset of the exception vector. See Table 7-1.
0 Exceptions are vectored to the physical address 0x000n_nnnn
1 Exceptions are vectored to the physical address 0xFFFn_nnnn
The reset value of IP is determined by the IIP bit (bit 2) in the hard reset conÞguration word. See
Section 12.3.1.1, ÒHard Reset ConÞguration Word.Ó Subsequent soft resets cause IP to revert to the
value latched during hard reset conÞguration.
1
26 IR Instruction address translation
0 Instruction address translation is disabled.
1 Instruction address translation is enabled.
For more information, see Chapter 9, ÒMemory Management Unit (MMU).Ó
1
27 DR Data address translation
0 Data address translation is disabled.
1 Data address translation is enabled.
For more information, see Chapter 9, ÒMemory Management Unit (MMU).Ó
28Ð29 Ñ Reserved
1
30 RI Recoverable exception (for system reset and machine check exceptions).
0 Exception is not recoverable.
1 Exception is recoverable.
For more information, see Chapter 7, ÒExceptions.Ó
1
31 L E Little-endian mode enable
0 The processor runs in big-endian mode.
1 The processor runs in little-endian mode.
1
These bits are loaded into SRR1 when an exception is taken. These bits are written back into the MSR when an
rÞ is executed.

5.1.2.3.2 Processor Version Register

The value of the PVR registerÕs version Þeld is 0x0050. The value of the revision Þeld is
incremented each time the core is revised.
5.1.3 MPC860-SpeciÞc SPRs
Table 5-2 and Table 5-9 list SPRs speciÞc to the MPC860. Debug registers, which have
additional protection, are described in Chapter 37, ÒSystem Development and Debugging.Ó
5-8
Description
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