Motorola MPC860 PowerQUICC User Manual page 654

Part V. The Communications Processor Module
22.3.5 Digital Phase-Locked Loop (DPLL) Operation
Each SCC channel includes a digital phase-locked loop (DPLL) for recovering clock
information from a received data stream. For applications that provide a direct clock source
to the SCC, the DPLL can be bypassed by selecting 1x mode for GSMR_L[RDCR, TDCR].
If the DPLL is bypassed, only NRZ or NRZI encodings are available. The DPLL must not
be used when an SCC is programmed to Ethernet and is optional for other protocols.
Figure 22-13 shows the DPLL receiver block; Figure 22-14 shows the transmitter block
diagram.
RXD
HSRCLK
22-22
RENC
RDCR
EDGE
DPLL
TSNC
Receiver
RINV
RXD
HSRCLK
RINV
RENC ¹ NRZI
D Q
CLK
Figure 22-13. DPLL Receiver Block Diagram
MPC860 PowerQUICC UserÕs Manual
Recovered Clock
HSRCLK
Carrier SNC
Noise
Hunting
Decoded Data
0
RCLK
1
S
1x Mode
0
SCCR Data
1
S
1x Mode
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