Motorola MPC860 PowerQUICC User Manual page 671

23.14 Fractional Stop Bits (Transmitter)
The asynchronous UART transmitter can be programmed to send fractional stop bits. The
FSB Þeld in the data synchronization register (DSR) determines the fractional length of the
last stop bit to be sent. FSB can be modiÞed at any time. If two stop bits are sent, only the
second is affected. Idle characters are always sent as full-length characters.
Bit 0 1 2
Field Ñ
Reset 0
R/W
Addr
Figure 23-5. Data Synchronization Register (DSR)
Table 23-6 describes DSR Þelds.
Bit Name
0 Ñ 0b0
1Ð4 FSB Fractional stop bits. For 16´ oversampling:
1111 Last transmitted stop bit 16/16. Default value after reset.
1110 Last transmitted stop bit 15/16.
É
1000 Last transmitted stop bit 9/16.
0xxx Invalid. Do not use.
For 32´ oversampling:
1111 Last transmitted stop bit 32/32. Default value after reset.
1110 Last transmitted stop bit 31/32.
É
0000 Last transmitted stop bit 17/32.
For 8´ oversampling:
1111 Last transmitted stop bit 8/8. Default value after reset.
1110 Last transmitted stop bit 7/8.
1101 Last transmitted stop bit 6/8.
1100 Last transmitted stop bit 5/8.
10xx Invalid. Do not use.
0xxx Invalid. Do not use.
The UART receiver can always receive fractional stop bits. The next characterÕs start bit can begin
any time after the three middle samples have been taken.
5Ð6 Ñ 0b11
7Ð8 Ñ 0b00
9Ð14 Ñ 0b111111
15 Ñ 0b0
MOTOROLA
3 4 5 6
FSB Ñ Ñ
1 1 1
0xA0E (DSR1), 0xA2E (DSR2), 0xA4E (DSR3), 0xA6E (DSR4)
Table 23-6. DSR Fields Descriptions
Chapter 23. SCC UART Mode
Part V. The Communications Processor Module
7 8 9 10
Ñ Ñ Ñ Ñ
0 0 1 1
R/W
Description
11 12 13 14
Ñ Ñ Ñ Ñ
1 1 1 1
23-11
15
Ñ
0