Motorola MPC860 PowerQUICC User Manual page 102

Part I. Overview
Name Type
BDIP Bidirectional
GPL_B5 Three-state
TS Bidirectional
Active Pull-up
TA Bidirectional
Active Pull-up
TEA Open-drain
BI Bidirectional
Active Pull-up
RSV Bidirectional
IRQ2 Three-state
3-4
Table 3-1. Signal Descriptions (Continued)
Burst Data in ProgressÑWhen accessing a slave device in the external bus, the
master on the bus asserts this signal to indicate that the data beat in front of the
current one is the one requested by the master. BDIP is negated before the expected
last data beat of the burst transfer.
General-Purpose Line B5ÑUsed by the memory controller when UPMB takes
control of the slave access.
Transfer StartÑThis signal is asserted by the bus master to indicate the start of a
bus cycle that transfers data to or from a slave device.
This signal is driven by the master only when it has gained the ownership of the bus.
Every master should negate this signal before the bus relinquish. TS requires the
use of an external pull-up resistor.
The MPC860 samples TS when it is not the external bus master to allow the memory
controller/PCMCIA interface to control the accessed slave device. It indicates that an
external synchronous master initiated a transaction.
Transfer AcknowledgeÑThis signal indicates that the slave device addressed in the
current transaction accepted data sent by the master (write) or has driven the data
bus with valid data (read). This is an output when the PCMCIA interface or memory
controller controls the transaction. The only exception occurs when the memory
controller controls the slave access by means of the GPCM and the corresponding
option register is instructed to wait for an external assertion of TA. Every slave device
should negate TA after a transaction ends and immediately three-state it to avoid bus
contention if a new transfer is initiated addressing other slave devices. TA requires
the use of an external pull-up resistor.
Transfer Error AcknowledgeÑThis signal indicates that a bus error occurred in the
current transaction. The MPC860 asserts TEA when the bus monitor does not detect
a bus cycle termination within a reasonable amount of time. Asserting TEA
terminates the bus cycle, thus ignoring the state of TA. TEA requires the use of an
external pull-up resistor.
Burst InhibitÑAsserting this signal indicates that the slave device addressed in the
current burst transaction cannot support burst transfers. It acts as an output when
the PCMCIA interface or the memory controller takes control of the transaction. BI
requires the use of an external pull-up resistor.
This is an active pull-up output. When the MPC860Õs memory controller responds to
a speciÞc transaction, it behaves as follows: if asserted, the MPC860 actively drives
this pin throughout the cycle; if negated, the MPC860 drives this pin high and then
three-states it. This line must be connected to VCC with a pull-up resistor. When the
MPC860Õs memory controller responds to a speciÞc transaction, other devices must
not attempt to drive this signal.Õ
ReservationÑThe MPC860 outputs this three-state signal in conjunction with the
address bus to indicate that the core initiated a transfer as a result of a stwcx. or
lwarx.
Interrupt Request 2ÑOne of eight external inputs that can request (by means of the
internal interrupt controller) a service routine from the core.
MPC860 PowerQUICC UserÕs Manual
Description
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