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CLKOUT/
GCLK2_50
GCLK1_50
GPL5
TS
Value
Controlled
by G5LS
Clock Phase
4
¥ GPL0 can be controlled by an address line speciÞed in MxMR[G0CLx]. To use this
feature, set G0H and G0L in the RAM word. For example, for a SIMM with multiple
banks, this address line can be used to switch between banks.
The state of GPL_x5 logic depends on the deÞned in Table 16-15. In the Þrst clock cycle
of the slave access, GPL_x5 reßects the value of ORx[G5LS]; in subsequent cycles, its state
is determined by G5T4 and G5T3 in the RAM word. If the UPMB controls slave access,
ORx[G5LA] can be used to select the active GPL_x5 signal. G5LS applies only to memory
requests and not to RAM words executed by the
periodic timer requests.
Controlling Machine
Memory
Slave Access
Access
Clock Cycle
GPCM
x
UPMA
First
Second,
third...
MOTOROLA
Value Controlled by G5T4 and G5T3 on UPM
1
2
3
RAM Word 1
Figure 16-42. Early GPL5 Control
Table 16-15. GPL_X5 Signal Behavior
ORx
RAM Word
G5LA G5LS G5T4 G5T3
N/A
N/A
x
x
x
0
x
x
1
x
x
0
x
1
x
x
0
x
1
Chapter 16. Memory Controller
4
1
command, exception, or memory
RUN
GPL_X5 Behavior at the Controlling Clock Edge
GPL_A5 and GPL_B5 do not change their value.
GPL_A5 is driven low at the falling edge of GCLK1_50.
GPL_A5 is driven high at the falling edge of GCLK1_50.
GPL_A5 is driven low at the falling edge of GCLK2_50 in
the current UPM cycle.
GPL_A5 is driven high at the falling edge of GCLK2_50 in
the current UPM cycle.
GPL_A5 is driven low at the falling edge of GCLK1_50 in
the current UPM cycle.
GPL_A5 is driven high at the falling edge of GCLK1_50 in
the current UPM cycle.
Part IV. Hardware Interface
RAM Word 2
16-41
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