Motorola MPC860 PowerQUICC User Manual page 544

Part V. The Communications Processor Module
18.2.3 CPM Timer Register Set
The following subsections discuss the CPM timer register set.
18.2.3.1 Timer Global ConÞguration Register (TGCR)
The timer global conÞguration register (TGCR) contains conÞguration parameters used by
all four timers. It allows simultaneous starting and stopping of any number of timers as long
as one bus cycle is used to access TGCR.
Bit 0 1 2
Field CAS4 FRZ4 STP4 RST4 GM2 FRZ3 STP3 RST3 CAS2 FRZ2 STP2 RST2 GM1 FRZ1 STP1 RST1
Reset
R/W
Addr
Figure 18-5. Timer Global Configuration Register (TGCR)
Table 18-1 describes the TGCR Þelds.
Bits Name
0 CAS4 Cascade timers.
0 Normal operation.
1 Timers 3 and 4 are cascaded to form a 32-bit timer.
1, 5, FRZx Freeze timer x.
9, 13 0 The corresponding timer ignores the FRZ state.
1 Stops the corresponding timer if the MPC860 enters FRZ state. FRZ state is entered in debug mode
as deÞned in Chapter 37, ÒSystem Development and Debugging.Ó
2, 6, STPx Stop timer x.
10, 0 Normal operation.
14 1 Stop the timer. This bit stops all clocks to the timer, except the U-bus interface clock allowing the
timer registers to be read or written. The clocks to the timer remain inactive until this bit is cleared or
a hardware reset occurs.
3, 7, RSTx Reset timer x.
11, The associated TMRx and TRRx registers should be initialized before enabling the timer with RSTx.
15 0 Reset the corresponding timer. Upon clearing this bit, all associated timer registers are reset.
1 Enable the corresponding timer if STP is cleared.
4 GM2 Gate mode for TGATE2. Valid only if TMR3[GE] or TMR4[GE] is set.
0 Restart gate mode. A falling edge of TGATE2 enables and restarts the count and a rising edge of
TGATE2 disables the count.
1 Normal gate mode. This mode is the same as 0, except the falling edge of TGATE2 does not restart
the count value in the TCN.
18-8
3 4 5 6
Table 18-1. TGCR Field Descriptions
MPC860 PowerQUICC UserÕs Manual
7 8 9 10
0
R/W
0x980
Description
11 12 13 14
MOTOROLA
15