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Figure
Number
36-27
DEMOD Function............................................................................................ 36-23
36-26
MOD Modulation Example ............................................................................. 36-23
36-28
DEMOD Function Descriptor.......................................................................... 36-24
36-30
LMS1 Function ................................................................................................ 36-25
36-29
DEMOD Modulation Example ........................................................................ 36-25
36-32
LMS2 Function ................................................................................................ 36-26
36-31
LMS1 Function Descriptor .............................................................................. 36-26
36-33
LMS2 Function Descriptor .............................................................................. 36-27
36-34
WADD Function.............................................................................................. 36-28
36-35
WADD Function Descriptor ............................................................................ 36-29
36-36
Example DSP ApplicationÑTx Filter ............................................................. 36-30
36-37
Core and CPM Implementation of Filter Example .......................................... 36-32
37-1
Watchpoints and Breakpoint Support in the Core ............................................. 37-9
37-2
Instruction Support General Structure ............................................................. 37-12
37-3
Load/Store Support General Structure............................................................. 37-13
37-4
Partially Supported Watchpoints/Breakpoint Example ................................... 37-17
37-5
Functional Diagram of the MPC860 Debug Mode Support ............................ 37-20
37-6
Debug Mode Logic Diagram ........................................................................... 37-21
37-7
Debug Mode Reset Configuration Timing Diagram ....................................... 37-22
37-8
Development Port/BDM Connector Pinout Options ....................................... 37-27
37-9
Asynchronous Clocked Serial Communications ............................................. 37-28
37-10
Synchronous Self-Clocked Serial Communications........................................ 37-29
37-11
Enabling Clock Mode after Reset .................................................................... 37-30
37-12
Download Procedure Code Example ............................................................... 37-34
37-13
Fast and Slow Download Procedure Loops ..................................................... 37-35
37-14
Comparator AÐD Value Register (CMPAÐCMPD) ........................................ 37-37
37-15
Comparator EÐF Value Registers (CMPEÐCMPF) ......................................... 37-38
37-16
Comparator GÐH Value Registers (CMPGÐCMPH)....................................... 37-38
37-17
Breakpoint Address Register (BAR) ............................................................... 37-38
37-18
Instruction Support Control Register (ICTRL)................................................ 37-39
37-19
Load/Store Support Comparators Control Register (LCTRL1)....................... 37-40
37-20
Load/Store Support AND-OR Control Register (LCTRL2)............................ 37-41
37-21
Breakpoint Counter Value and Control Registers (COUNTA/COUNTB)...... 37-44
37-22
Interrupt Cause Register (ICR) ........................................................................ 37-44
37-23
Debug Enable Register (DER)......................................................................... 37-46
38-1
Test Logic Block Diagram................................................................................. 38-2
38-2
TAP Controller State Machine........................................................................... 38-3
38-3
Output Signal Boundary Scan Cell (Output Cell).............................................. 38-4
38-4
Observe-Only Input Signal Boundary Scan Cell (Input Cell) ........................... 38-4
38-5
Input/Output Control Boundary Scan Cell (I/O Control Cell)........................... 38-5
38-6
Bidirectional (I/O) Signal Boundary Scan Cell ................................................. 38-5
38-7
Bypass Register.................................................................................................. 38-7
A-1
TLE Mode Mechanisms..................................................................................... A-3
MOTOROLA
ILLUSTRATIONS
Title
Illustrations
Page
Number
xlix
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