Motorola MPC860 PowerQUICC User Manual page 610

Part V. The Communications Processor Module
CE=1
L1CLK
L1SYNC
L1TXD
(Bit-0)
L1ST
(On Bit-0)
L1SYNC
L1TXD
(Bit-0)
L1ST
(On Bit-0)
L1SYNC
L1TXD
(Bit-0)
L1ST
(On Bit-0)
L1SYNC
L1TXD
(Bit-0)
L1ST
(On Bit-0)
Figure 21-18. Frame Transfers when xFSD = 0 and CE = 1
Figure 21-19 shows SIMODE[FE] behavior when SIMODE[CE] and SIMODE[xFSD] are
zero.
21-22
The L1ST is Driven from Sync.
Data is Driven from Clock Low.
Rx Sampled Here
L1ST is Driven from Clock High.
Both Data Bit-0 and L1ST are
Driven from Sync.
Rx Sampled Here
L1ST and Data Bit-0 is Driven
from Clock Low.
MPC860 PowerQUICC UserÕs Manual
xFSD=0
(FE=0)
(FE=0)
(FE=1)
(FE=1)
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