Motorola MPC860 PowerQUICC User Manual page 533

¥ Chapter 34, ÒParallel I/O Ports,Ó describes the four general-purpose I/O portsÑA,
B, C, and D. Each signal in the I/O ports can be conÞgured as a general-purpose I/
O signal or as a signal dedicated to supporting communications devices, such as
SMCs and SCCs.
¥ Chapter 35, ÒCPM Interrupt Controller,Ó describes how the CPM interrupt controller
(CPIC) accepts and prioritizes the internal and external interrupt requests from the
CPM blocks and passes them to the system interface unit (SIU). The CPIC also
provides a vector during the core interrupt acknowledge cycle.
¥ Chapter 36, ÒDigital Signal Processing,Ó describes the CPMÕs hardware and library
functions that support DSP applications.
Suggested Reading
This section lists additional reading that provides background for the information in this
manual as well as general information about the PowerPC architecture.
MPC8xx Documentation
Supporting documentation for the MPC860 can be accessed through the world-wide web
at http://www.motorola.com/SPS/RISC/netcomm. This documentation includes technical
speciÞcations, reference materials, and detailed applications notes.
PowerPC Documentation
The PowerPC documentation is organized in the following types of documents:
¥ Programming environments manualsÑThese books provide information about
resources deÞned by the PowerPC architecture that are common to PowerPC
processors. There are two versions, one that describes the functionality of the
combined 32- and 64-bit architecture models and one that describes only the 32-bit
model.
Ñ PowerPC Microprocessor Family: The Programming Environments, Rev 1
(Motorola order #: MPCFPE/AD)
Ñ PowerPC Microprocessor Family: The Programming Environments for 32-Bit
Microprocessors, Rev. 1 (Motorola order #: MPCFPE32B/AD)
¥ PowerPC Microprocessor Family: The Bus Interface for 32-Bit Microprocessors
(Motorola order #: MPCBUSIF/AD) provides a detailed functional description of
the 60x bus interface, as implemented on the PowerPC 601ª, 603, and 604 family
of PowerPC microprocessors. This document is intended to help system and chip set
developers by providing a centralized reference source to identify the bus interface
presented by the 60x family of PowerPC microprocessors.
¥ PowerPC Microprocessor Family: The ProgrammerÕs Reference Guide
(Motorola order #: MPCPRG/D) is a concise reference that includes the register
summary, memory control model, exception vectors, and the PowerPC instruction
set.
MOTOROLA Part V. The Communications Processor Module
Part V. The Communications Processor Module
V-iii