Motorola MPC860 PowerQUICC User Manual page 406

Part IV. Hardware Interface
timing relationship between GCLKx and GCLKx_50 is shown in Figure 15-8.
GCLK1
GCLK2
GCLK1_50
(EBDF=00)
GCLK2_50
(EBDF=00)
CLKOUT
(EBDF=00)
GCLK1_50
(EBDF=01)
GCLK2_50
(EBDF=01)
CLKOUT
(EBDF=01)
Figure 15-8. Memory Controller and External Bus Clocks Timing Diagram for
If SCCR[EBDF]=0, the duty cycle of both GCLK1_50 and GCLK2_50 is 50%. However,
if SCCR[EBDF]=1, the duty cycle of GCLK2_50 is 50%, but the duty cycle of GCLK1_50
is 37.5%, as shown in Figure 15-8.
The low-power frequency dividers described in Section 15.3.1.1, ÒThe Internal General
System Clocks (GCLK1C, GCLK2C, GCLK1, GCLK2)Ó also effect the frequency and
duty cycle of GCLK1_50, GCLK2_50, and CLKOUT. For an example of this, see
Figure 15-9.
15-12
EBDF=0 and EBDF=1
MPC860 PowerQUICC UserÕs Manual MOTOROLA