Motorola MPC860 PowerQUICC User Manual page 366

Part IV. Hardware Interface
supplies/samples the address of the Þrst word of the burst and asserts the burst-inhibit signal
(BI) with TA for the Þrst transfer of the burst access. The MPC860 responds by terminating
the burst and accessing the rest of the 16-byte block, using three read/write cycles (each one
for a word) for a 32-bit port-width slave, seven read/write cycles for a 16-bit port-width
slave, or Þfteen read/write cycles for a 8-bit port-width slave.
The general case of burst transfers assumes that external memory has a 32-bit port size. The
MPC860 provides an effective mechanism for interfacing with 16-bit port size memories
and 8-bit port size memories allowing bursts transfers to these devices when they are
controlled by the internal memory controller. In this case, the MPC860 attempts to initiate
a burst transfer as in the normal case. If, in a cycle before the TA is asserted for the Þrst
beat, the memory controller responds that the port size is 16-/8-bits and that the burst is
accepted, the MPC860 completes a 8-/16-beat burst. Each data beat effectively transfers
only 2/1 bytes. Note that this 8-/16-beat burst is considered an atomic transaction, so the
MPC860 will not allow other unrelated master accesses or bus arbitration between
transfers.
14.4.4 Burst Operations
The MPC860 burst mechanism uses additional signals to the basic protocol: BURST
indicates that the cycle is a burst cycle, burst data in progress (BDIP) indicates the duration
of the burst data, and burst inhibit (BI) indicates whether the slave supports bursts. Along
with asserting TS, the master drives the address, address attributes, and BURST signals to
indicate that a burst transfer is being initiated. Slaves that support bursting negate BI. If the
slave cannot burst, it asserts the BI. During the data phase of a burst write cycle the master
drives the data. It also asserts BDIP if it intends to drive the data beat after the current one.
When the slave has received the data, it asserts TA to indicate to the master that it is ready
for the next transfer. The master again drives the next data and asserts or negates BDIP. If
the master does not intend to drive another data beat, it negates BDIP to indicate to the slave
that the next data beat is the last one in the burst write.
Bursts performed by MPC860 internal masters are always transfer 16 bytes. The MPC860
memory controller responds only to Þxed-length bursts (also typically programmed to be
16 bytes). Therefore, devices in an MPC860 system should attempt only 16-byte burst
transfers except for external masters with a dedicated chip select, such as an external
MPC603 that bursts to a chip select programmed for a 32-byte burst.
During the data phase of a burst read cycle, the master receives data from the addressed
slave. If the master needs more than one data, it asserts BDIP. When the data is received
prior to the last data, the master deasserts BDIP. Thus, the slave stops driving new data after
it received the negation of BDIP at the rising clock edge.
In the case of 32-bit port size, the burst includes 4 beats. When the port size is 16 bits and
controlled by the internal memory controller, the burst includes 8 beats. When the port size
is 8 bits and controlled by the internal memory controller, the burst includes 16 beats. The
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