Motorola MPC860 PowerQUICC User Manual page 873

Table 33-9. PIP TxBD Status and Control Field Descriptions (Continued)
Bits Name
12 F Fault.
0 The FAULT status line has remained negated during transmission.
1 The FAULT status line has been asserted during transmission.
13 PE Paper error.
0 The PERROR status line has remained negated during transmission.
1 The PERROR status line has been asserted during transmission.
14 S Select error.
0 The SELECT status line has remained asserted during transmission.
1 The SELECT status line has been negated during transmission.
15 Ñ Reserved and should be cleared.
33.5.2 The PIP Rx Buffer Descriptor (RxBD)
Using buffer descriptors, the CP conÞrms reception or indicates error conditions so the core
knows which buffers have been serviced. Figure 33-10 shows the PIP RxBD.
0 1
Offset + 0 E Ñ
Offset + 2
Offset + 4
Offset + 6
Figure 33-10. PIP Rx Buffer Descriptor (RxBD)
Table 33-10 describes the PIP RxBD status and control Þeld. The data length and buffer
pointer are described in Section 33.5, ÒPIP Buffer Descriptors,Ó above.
Table 33-10. PIP RxBD Status and Control Field Descriptions
Bits Name
0 E Empty.
0 The buffer associated with this descriptor is full or stopped receiving data because an error occurred.
The core can read or write any Þelds of this RxBD. The CP cannot use this BD while E is 0.
1 The buffer associated with this BD is empty or is receiving data. Once E is set, the core should not
write any Þelds of this RxBD.
1 Ñ Reserved and should be cleared.
2 W Wrap (last buffer descriptor in RxBD table). The number of RxBDs in the table is determined only by the
W bit and space constraints of the dual-port RAM.
0Not the last BD in the RxBD table.
1 The last BD in the RxBD table. After this BD is processed, the current RxBD pointer wraps to the top
of the RxBD table (RBASE).
3 I Interrupt.
0 No interrupt is generated after this buffer is Þlled.
1 PIPE[RXB] is set when the CP Þlls this buffer, signaling the core to process the buffer. The RXB bit
causes an interrupt if not masked.
MOTOROLA
2 3 4 5
W I C Ñ CM
Chapter 33. Parallel Interface Port
Part V. The Communications Processor Module
Description
6 7 8 9 10
SL
Data Length
Rx Buffer Pointer
Description
11 12 13 14 15
Ñ
33-13