Motorola MPC860 PowerQUICC User Manual page 282

Part III. Configuration
Table 11-3. SIUMCR Field Descriptions (Continued)
Bits Name
14 FRC FRZ pin conÞguration. ConÞgures the functionality of FRZ/IRQ6.
0 FRZ/IRQ6 functions as FRZ.
1 FRZ/IRQ6 functions as IRQ6.
15 DLK Debug register lock. If DLK is set, bits 8Ð15 are locked and writes to those bits are no longer
performed. These bits can be written once the internal FRZ signal is asserted, regardless of the
state of DLK. Cleared at reset.
16 OPAR Odd parity. Used to program odd or even parity. Also used to generate parity errors for testing
purposes by writing the memory with OPAR = 1 and reading the memory with OPAR = 0.
17 PNCS Parity enable for nonmemory controller regions. Enables parity generation/checking for memory
regions not controlled by the memory controller.
18 DPC Data parity pins conÞguration. ConÞgures the functionality of DP[0Ð3]/IRQ[3Ð6].
0 DP[0Ð3]/IRQ[3Ð6] functions as IRQ[3Ð6].
1 DP[0Ð3]/IRQ[3Ð6] functions as DP[0Ð3].
19 MPRE Multiprocessors reservation enable.
0 RSV/IRQ2 functions as IRQ2.
1 RSV/IRQ2 functions as RSV. The interprocessor reservation protocol is enabled. RSV functions
as deÞned in Section 14.4.9, ÒMemory Reservation.Ó
20Ð21 MLRC Multi-level reservation control. ConÞgures the functionality of KR/RETRY/IRQ4/SPKROUT.
00 KR/RETRY/IRQ4/SPKROUT functions as IRQ4.
01 KR/RETRY/IRQ4/SPKROUT is three-stated.
10 KR/RETRY/IRQ4/SPKROUT functions as KR/RETRY.
11 KR/RETRY/IRQ4/SPKROUT functions as SPKROUT.
22 AEME Asynchronous external master enable. ConÞgures how the memory controller refers to external
asynchronous masters initiating a transaction. If AEME = 1, the memory controller interprets any
assertion of AS as an external asynchronous master initiating a transaction. If it is reset, the memory
controller ignores the value of AS.
23 SEME Synchronous external master enable. ConÞgures how the memory controller refers to synchronous
external masters initiating a transaction. If SEME = 1, the memory controller interprets any assertion
of TS that the MPC860 does not drive as a synchronous external master initiating a transaction.
24 BSC ConÞgures how memory controller and PCMCIA interface byte selects and strobes are conÞgured.
0 BS_A[0Ð3] are driven just on their dedicated pins.
WE0/BS_B0/IORD is driven on its dedicated pin.
WE1/BS_B1/IOWR is driven on its dedicated pin.
WE2/BS_B2/PCOE is driven on its dedicated pin.
WE3/BS_B3/PCWE is driven on its dedicated pin.
1 Assertion of either BS_A0, WE0, BS_B0 or IORD is driven on BS_A0 and WE0/BS_B0/IORD.
Assertion of either BS_A1, WE1, BS_B1 or IOWR is driven on BS_A1 and WE1/BS_B1/IOWR.
Assertion of either BS_A2, WE2, BS_B2 or PCOE is driven on BS_A2 and WE2/BS_B2/PCOE.
Assertion of either BS_A3, WE3, BS_B3 or PCWE is driven on BS_A3 and WE3/BS_B3/PCWE.
25 GB5E GPL_B5 enable
0 The BDIP functionality is active.
1 The GPL_B5 of the memory controller functionality is active
26 B2DD Bank 2 double drive. If this bit is set, CS2 is reßected on GPL_x2.
27 B3DD Bank 3 double drive. If this bit is set, CS3 is reßected on GPL_x3.
28Ð31 Ñ Reserved, should be cleared.
11-8
Description
MPC860 PowerQUICC UserÕs Manual MOTOROLA