Motorola MPC860 PowerQUICC User Manual page 42

Figure
Number
16-54 Single-Beat Read Access to Page-Mode DRAM............................................. 16-61
16-55 Single-Beat Write Access to Page Mode DRAM ............................................ 16-62
16-56 Burst Read Access to Page-Mode DRAM (No LOOP)................................... 16-63
16-57 Burst Read Access to Page-Mode DRAM (LOOP)......................................... 16-64
16-58 Burst Write Access to Page-Mode DRAM (No LOOP).................................. 16-65
16-59 Burst Write Access to Page-Mode DRAM (LOOP)........................................ 16-66
16-60 Refresh Cycle (CAS before RAS) to Page-Mode DRAM............................... 16-67
16-61 Exception Cycle ............................................................................................... 16-68
16-62 Optimized DRAM Burst Read Access ............................................................ 16-69
16-63 EDO DRAM Interface Connection.................................................................. 16-70
16-64 EDO DRAM Single-Beat Read Access........................................................... 16-72
16-65 EDO DRAM Single-Beat Write Access .......................................................... 16-73
16-66 EDO DRAM Burst Read Access ..................................................................... 16-74
16-67 EDO DRAM Burst Write Access .................................................................... 16-75
16-68 EDO DRAM Refresh Cycle (CAS before RAS) ............................................. 16-76
16-69 EDO DRAM Exception Cycle......................................................................... 16-77
16-70 Blank Work Sheet for a UPM.......................................................................... 16-78
17-1 System with Two PCMCIA Sockets.................................................................. 17-2
17-2 Internal DMA Request Logic............................................................................. 17-7
17-3 PCMCIA Interface Input Pins Register (PIPR) ................................................. 17-8
17-4 PCMCIA Interface Status Changed Register (PSCR) ....................................... 17-9
17-5 PCMCIA Interface Enable Register (PER)...................................................... 17-10
17-6 PCMCIA Interface General Control Register B (PGCRx) .............................. 17-12
17-7 PCMCIA Base Register (PBR)........................................................................ 17-13
17-8 PCMCIA Option Register 0Ð7 (POR0ÐPOR7)................................................ 17-13
17-9 PCMCIA Single-Beat Read Cycle PRS = 0 PSST = 1 PSL = 3 PSHT = 1..... 17-16
17-10 PCMCIA Single-Beat Read Cycle PRS = 0 PSST = 2 PSL = 4 PSHT = 1..... 17-17
17-11 PCMCIA Single-Beat Read Cycle PRS = 0 PSST = 1 PSL = 3 PSHT = 0..... 17-18
17-12 PCMCIA Single-Beat Write Cycle PRS = 2 PSST = 1 PSL = 3 PSHT = 1 .... 17-19
17-13 PCMCIA Single-Beat Write Cycle PRS = 3 PSST = 1 PSL = 4 PSHT = 3 .... 17-20
17-14 PCMCIA Single-Beat Write with Wait PRS = 3 PSST = 1 PSL = 3
PSHT = 0 ......................................................................................................... 17-21
17-15 PCMCIA Single-Beat Read with Wait PRS = 3 PSST = 1 PSL = 3
PSHT =1 .......................................................................................................... 17-22
17-16 PCMCIA I/O Read PPS = 1 PRS = 3 PSST = 1 PSL = 2 PSHT = 0............... 17-23
17-17 PCMCIA I/O Read PPS = 1 PRS = 3 PSST = 1 PSL = 2 PSHT = 0............... 17-24
17-18 PCMCIA DMA Read Cycle PRS = 4 PSST = 1 PSL = 3 PSHT = 0 .............. 17-25
18-1 CPM Block Diagram.......................................................................................... 18-2
18-2 MPC860 Application Design Example.............................................................. 18-4
18-3 CPM Timer Block Diagram............................................................................... 18-5
18-4 Timer Cascaded Mode Block Diagram.............................................................. 18-7
18-5 Timer Global Configuration Register (TGCR).................................................. 18-8
18-6 Timer Mode Registers (TMR1ÐTMR4)............................................................. 18-9
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ILLUSTRATIONS
Title
MPC860 PowerQUICC UserÕs Manual
Page
Number
MOTOROLA