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Figure
Number
14-25
Termination Signals Protocol Basic Connection ............................................. 14-34
14-26
Termination Signals Protocol Timing Diagram............................................... 14-34
14-27
Reservation On Local Bus ............................................................................... 14-36
14-28
Reservation on Multilevel Bus Hierarchy........................................................ 14-37
14-29
Retry Transfer TimingÐInternal Arbiter .......................................................... 14-38
14-30
Retry Transfer TimingÐExternal Arbiter ......................................................... 14-39
14-31
Retry on Burst Cycle........................................................................................ 14-40
15-1
Clock Source and Distribution........................................................................... 15-2
15-2
Clock Module Components ............................................................................... 15-3
15-3
.Crystal Circuit Examples .................................................................................. 15-5
15-4
SPLL Block Diagram......................................................................................... 15-6
15-5
Clock Dividers ................................................................................................. 15-10
15-6
Low-power dividers for GCLKx ..................................................................... 15-11
15-7
Divided System Clocks (GCLKx) Timing Diagram ....................................... 15-11
15-8
Memory Controller and External Bus Clocks Timing Diagram for
EBDF=0 and EBDF=1..................................................................................... 15-12
15-9
Memory Controller and External Bus Clocks Timing Diagram for
(CSRC=0 and DFNH=1) or (CSRC=1 and DFNL=0) .................................... 15-13
15-10
BRGCLK Divider ............................................................................................ 15-14
15-11
SYNCCLK Divider.......................................................................................... 15-15
15-12
MPC860 Power Rails....................................................................................... 15-17
15-13
MPC860 Low-Power Mode Flowchart............................................................ 15-20
15-14
Software-initiated Power-down Configuration................................................ 15-25
15-15
SCCR ............................................................................................................... 15-27
15-16
PLL, Low-Power, and Reset Control Register (PLPRCR).............................. 15-30
16-1
Memory Controller Block Diagram................................................................... 16-3
16-2
Memory Controller Machine Selection ............................................................. 16-4
16-3
Simple System Configuration ............................................................................ 16-5
16-4
Basic Memory Controller Operation ................................................................. 16-6
16-5
Base Registers (BRx)......................................................................................... 16-9
16-6
BR0 Reset Defaults............................................................................................ 16-9
16-7
Option Registers (ORx) ................................................................................... 16-11
16-8
OR0 Reset Defaults.......................................................................................... 16-11
16-9
Memory Status Register (MSTAT) ................................................................. 16-13
16-10
Machine A Mode Register/Machine B Mode Registers (MxMR)................... 16-14
16-11
Memory Command Register (MCR) ............................................................... 16-15
16-12
Memory Data Register (MDR) ........................................................................ 16-16
16-13
Memory Address Register (MAR)................................................................... 16-17
16-14
Memory Periodic Timer Prescaler Register (MPTPR).................................... 16-17
16-15
GPCM-to-SRAM Configuration...................................................................... 16-18
16-16
GPCM Peripheral Device Interface ................................................................. 16-20
16-17
GPCM Peripheral Device Basic Timing (ACS = 1x and TRLX = 0).............. 16-20
16-18
GPCM Memory Device Interface.................................................................... 16-21
xl
ILLUSTRATIONS
Title
MPC860 PowerQUICC UserÕs Manual
Page
Number
MOTOROLA
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