Motorola MPC860 PowerQUICC User Manual page 81

¥ Interrupts
Ñ Seven external interrupt request (IRQ) lines
Ñ 12 port pins with interrupt capability
Ñ 23 internal interrupt sources
Ñ Programmable priority between SCCs
Ñ Programmable highest priority request
¥ Communications processor module (CPM)
Ñ RISC controller
Ñ Communication-speciÞc commands (for example,
ENTER HUNT MODE
Ñ Up to 384 buffer descriptors (BDs)
Ñ Supports continuous mode transmission and reception on all serial channels
Ñ Up to 5 Kbytes of dual-port RAM
Ñ 16 serial DMA (SDMA) channels
Ñ Three parallel I/O registers with open-drain capability
¥ On-chip 16 x 16 multiply accumulate controller (MAC)
Ñ One operation per clock (two clock latency, one clock blockage)
Ñ MAC operates concurrently with other instructions
Ñ FIR loop: four clocks per four multiplies
¥ Four baud rate generators
Ñ Independent (can be connected to any SCC or SMC)
Ñ Allow changes during operation
Ñ Autobaud support option
¥ Four SCCs (serial communication controllers)
Ñ Ethernet/IEEE 802.3 optional on SCC1Ð4, supporting full 10-Mbps operation
(Available only on specially programmed devices)
Ñ HDLC/SDLC
Ñ HDLC bus (implements an HDLC-based local area network (LAN))
Ñ Asynchronous HDLC to support PPP (point-to-point protocol)
Ñ AppleTalk
Ñ Universal asynchronous receiver transmitter (UART)
Ñ Synchronous UART
Ñ Serial infrared (IrDA)
Ñ Binary synchronous communication (BISYNC)
Ñ Totally transparent (bit streams)
Ñ Totally transparent (frame based with optional cyclic redundancy check (CRC))
MOTOROLA
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Chapter 1. MPC860 Overview
GRACEFUL STOP TRANSMIT
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Part I. Overview
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1-3