Motorola MPC860 PowerQUICC User Manual page 465

Table 16-13. RAM Word Bit Settings (Continued)
Bit Name
30 TODT Turn-on disable timer. Controls the disable timer mechanism. This bit has meaning only in RAM
words for which UTA = 0; otherwise it is a donÕt care.
0 The disable timer is turned off.
1 The disable timer for the current bank is activated preventing a new access to the same bank
(when controlled by the UPMs) until the disable timer expires. For example, precharge time.
31 LAST Last. If this bit is set, it is the last RAM word in the program.
0 The UPM continues executing RAM words.
1 The service to the UPM request is done.
16.6.4.2 Chip-Select Signals (CxTx)
If BRx[MS] of the accessed bank selects a UPM on the currently requested cycle the UPM
manipulates the CS signal for that bank with timing as speciÞed in the UPM RAM word.
The selected UPM affects only assertion and negation of the appropriate CS signal. The
state of the selected CSx signal of the corresponding bank depends on the value of each
CSTn bit.
Figure 16-40 and the timing diagrams in Figure 16-36 and Figure 16-37 shows how UPMs
control CS signals.
UPMA
UPMB
GPCM
16.6.4.3 Byte-Select Signals (BxTx)
BRx[MS] of the accessed memory bank selects a UPM on the currently requested cycle.
The selected UPM affects only the assertion and negation of the appropriate BS signal; its
timing as speciÞed in the RAM word. The state of each BS[0Ð3] signal depends on the
value of each BSTx bit and the values of BRx[PS], TSIZn, and A[30Ð31] in the current
cycle.The BS signals are also controlled by the port size of the accessed bank, the transfer
size of the transaction, and the address accessed. Figure 16-41 shows how UPMs control
BS signals.
MOTOROLA
Description
Bank Selected
MS[0Ð1] in BRx
MUX
MS[0Ð1] Machine
00 GPCM
01 Ð
10 UPMA
11 UPMB
Figure 16-40.CS Signal Selection
Chapter 16. Memory Controller
Part IV. Hardware Interface
Switch CS0
CS1
CS2
CS3
CS4
CS5
CS6
CS7
16-39