Motorola MPC860 PowerQUICC User Manual page 185

The system call exception causes the next instruction to be fetched from offset 0x00C00
from the physical base address indicated by the new setting of MSR[IP]. As with most other
exceptions, this exception is context-synchronizing. Refer to Section 6.2.2.3.1, ÒContext
Synchronization,Ó regarding actions performed by a context-synchronizing operation.
Table 7-10. Register Settings after a System Call Exception
Register
SRR0 Set to the effective address of the instruction following the System Call instruction
SRR1 0
1Ð4
5Ð9
10Ð15
16Ð31
Note that depending on the implementation, reserved bits in the MSR may not be copied to SRR1.
MSR POW 0
ILE Ñ
EE 0
PR 0
When a system call exception is taken, instruction execution resumes at offset 0x00C00
from the physical base address indicated by MSR[IP].
7.1.2.10 Trace Exception (0x00D00)
A trace exception occurs if MSR[SE] = 1 and any instruction except rÞ is successfully
completed or if MSR[BE] = 1 and a branch is completed. Notice that the trace exception
does not occur after an instruction that causes an exception. The monitor/debugger software
must change the vectors of other possible exception addresses to single-step these
instructions. If this is unacceptable, other debug features can be used. See Chapter 37,
ÒSystem Development and Debugging,Ó for more information. Table 7-11 shows register
settings for trace exceptions.
Table 7-11. Register Settings after a Trace Exception
Register
SRR0 Set to the EA of the instruction following the executed instruction.
SRR1 1Ð4 0
10Ð15 0
Others Loaded from MSR[16-31]. SRR1[30] is cleared only by loading a zero from MSR[RI].
MSR IP No change
ME No change
LE Copied from the ILE setting of the interrupted process
Others 0
Execution resumes at offset 0x00D00 from the base address indicated by MSR[IP].
MOTOROLA
Setting Description
Loaded with equivalent bits from the MSR
Cleared
Loaded with equivalent bits from the MSR
Cleared
Loaded with equivalent bits from the MSR
FP 0
ME Ñ
SE 0
BE 0
Chapter 7. Exceptions
Part II. PowerPC Microprocessor Module
IP Ñ
IR 0
DR 0
RI 0
Setting
LE Set to value of ILE
7-11