Motorola MPC860 PowerQUICC User Manual page 436

Part IV. Hardware Interface
Table 16-3 describes BRx Þelds.
Bits Name
0Ð16 BA Base address. Compared to A[0Ð16] to determine if a memory bank controlled by the memory
controller is being accessed by an internal or external bus master. Used in conjunction with ORx[AM].
17Ð19 AT Address type. Can be used to limit accesses to the memory bank to a certain address space type,
AT[0Ð2]. Note that for internal bus masters, AT[0Ð2] are sampled from the bus. For external bus
masters, AT[0Ð2] are not sampled on the external bus and instead default to 0b100. Used in
conjunction with the ORx[ATM].
20Ð21 PS Port size. SpeciÞes the port size of the memory region. After system reset, the value of BR0[PS]
depends on BPS in the hard reset conÞguration word, described in Section 12.3.1.1.
00 32-bit port size.
01 8-bit port size.
10 16-bit port size.
11 Reserved.
22 PARE Parity enable. Used to enable parity checking on this bank.
0 Parity checking is disabled.
1 Parity checking is enabled.
23 WP Write-protect. Can be used to restrict write accesses within the address range of a BR.
0 Both read and write accesses are allowed.
1 Only read accesses are allowed. The memory controller does not assert CSx and TA on write
cycles to this memory bank. Attempting to write to the memory bank causes MSTAT[WPER] to be
set. The write access is not terminated by the memory controller; however, it is terminated by a TEA
assertion from the bus monitor if the bus monitor is enabled.
24Ð25 MS Machine select. Selects the machine for handling memory operations.
00 GPCM.
01 Reserved.
10 UPMA.
11 UPMB.
26Ð30 Ñ Reserved, should be cleared.
31 V Valid. Indicates that the contents of the BRx and ORx are valid. The reset value of BR0[V] depends on
the BDIS bit value in the hard reset conÞguration word, described in Section 12.3.1.1.
0 This bank is invalid. An attempt to access this region can cause a bus monitor timeout.
1 This bank is valid. The CS signal does not assert until V is set.
16.4.2 Option Registers (ORx)
The option registers (OR0ÐOR7), shown in Figure 16-7, contain the address and address
type mask bit for address bus comparison. It also includes all GPCM parameters.
16-10
Table 16-3. BRx Field Descriptions
Description
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