Motorola MPC860 PowerQUICC User Manual page 982

Part VI. Debug and Test
Table 37-12. Status/Data Shifted Out of Development Port Shift Register
Rea Status
dy [0Ð1]
Bit 0
(0) 0 0
(0) 0 1 Freeze
status
(0) 1 0
(0) 1 1
1
The freeze status is 1 when the core is in debug mode. Otherwise it is 0.
2
The ÒDownload Procedure In ProgressÓ status is asserted (0) when the debug port in the download procedure is
negated. Otherwise it is set to 1.
The ÒValid Data from CoreÓ and ÒCore InterruptÓ functions cannot occur in trap enable
mode. When not in debug mode, the sequencing error encoding indicates that the
transmission from the external development tool was a debug mode transmission. When a
sequencing error occurs the development port ignores the data shifted in while the
sequencing error is shifting out and is treated as a no-op function. The null output encoding
is used to indicate that the previous transmission had no associated errors. When not in
debug mode, ready is asserted at the end of each transmission. If debug mode is not enabled
and transmission errors can be guaranteed not to occur, the status output is not needed.
37.3.2.5 Development Port Serial CommunicationsÐDebug Mode
Debug mode is a superset of trap enable mode. All of the trap enable mode functionality is
available, with the following additions.
¥ In debug mode, the development port starts communications by setting DSDO low
to indicate that the core is trying to read an instruction from DPIR or data from
DPDR.
¥ When the core writes data to the port to be shifted out, the ready bit is not set.
Instead, the port waits for the core to read the next instruction before asserting ready.
This allows duplex operation of the serial port and lets the port control all
transmissions from the external development tool. After detecting this ready status
the external development tool begins transmitting to the development port with a
start bit (logic high) on DSDI.
37.3.2.5.1 Serial Data Into Development Port
In debug mode the 35 bits of the development port shift register are interpreted as a
start/ready bit, a mode/status bit, a control/status bit, and 32 bits of data. All instructions
and data for the core are sent with the mode bit cleared indicating a 32-bit data Þeld.
Table 37-13 shows the encoding of data shifted into the development port shift register
through DSDI. Data values in the last two functions other than those speciÞed are reserved.
37-32
Bit 1 Bits 2Ð31 or 2Ð6 Depending on Input Mode
Download
1
procedure
2
in progress
MPC860 PowerQUICC UserÕs Manual
Data
Data
1s
1s
1s
Function
Valid data from
core
Sequencing error
Core interrupt
Null
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