Embedded Powerpc Core - Motorola MPC860 PowerQUICC User Manual

Part I. Overview

1.3 Embedded PowerPC Core

The core is compliant with the UISA (user instruction set architecture) portion of the
PowerPC architecture. It is a fully static design that has an integer unit (IU) and a load/store
unit (LSU). It executes all integer and load/store operations in hardware. The core supports
integer operations on a 32-bit internal data path and 32-bit arithmetic hardware. The core
interface to the internal and external buses is 32 bits. The core can operate on 32-bit external
operands with one bus cycle.
The IU uses 32, 32-bit GPRs for source and target operands. Typically, it can execute one
integer instruction each clock cycle. Each element in the integer block is clocked only when
valid data is present in the data queue ready for operation. This assures that power
consumption of the device is held to the absolute minimum required for operation.
The core is integrated with MMUs as well as 4-Kbyte instruction and data caches. Each
MMU provides a 32 entry, fully associative instruction and data TLB, with multiple page
sizes of 4, 16, 512, and 256 Kbytes and 8 Mbytes. It supports 16 virtual address spaces with
8 protection groups. Three special scratch registers support software table walk and update.
The instruction cache is 4 Kbytes, two-way, set associative with physical addressing. It
allows single-cycle access on hits with no added latency for misses. It has four words per
block, supporting a four-beat burst line Þll using an LRU (least recently used) replacement
algorithm. The cache can be locked on a per cache block basis for application-critical
routines.
The data cache is 4 Kbytes, two-way, set associative with physical addressing. It allows
single-cycle accesses on hits with one added clock latency for misses. It has four words per
cache block, supporting burst line Þll using LRU replacement. The cache can be locked on
a per block basis for application critical routines. The data cache can be programmed to
support copy-back or write-through via the MMU. The inhibit mode can be programmed
per MMU page.
The core contains a much improved debug interface that provides superior debug
capabilities without causing any degradation in the speed of operation. This interface
supports six watchpoint pins that are used to detect software events. Internally it has eight
comparators, four of which operate on the effective address on the address bus. The
remaining four comparators are split, with two comparators operating on the effective
address on the data address bus, and two comparators operating on the data bus. The core
can compare using =, ¹, <, > conditions to generate watchpoints. Each watchpoint can then
generate a break point that can be programmed to trigger in a programmable number of
events.
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