Motorola MPC860 PowerQUICC User Manual page 96

Part I. Overview
Table 2-1. MPC860 Internal Memory Map (Continued)
Offset
A37 SCCS2ÑSCC2 status register
A38ÐA3F Reserved
A40 GSMR_L3ÑSCC3 general mode register
A44 GSMR_H3ÑSCC3 general mode register
A48 PSMR3ÑSCC3 protocol speciÞc mode register
A4AÐA4B Reserved
A4C TODR3ÑSCC3 transmit on demand register
A4E DSR3ÑSCC3 data synchronization register
A50 SCCE3ÑSCC3 event register
A52ÐA53 Reserved
A54 SCCM3ÑSCC3 mask register
A56 Reserved
A57 SCCS3ÑSCC3 status register
A58ÐA5F Reserved
A60 GSMR_L4ÑSCC4 general mode register
A64 GSMR_H4ÑSCC4 general mode register
A68 PSMR4ÑSCC4 protocol speciÞc mode register
A6AÐA6B Reserved
A6C TODR4ÑSCC4 transmit on demand register
A6E DSR4ÑSCC4 data synchronization register
A70 SCCE4ÑSCC4 event register
A72ÐA73 Reserved
A74 SCCM4ÑSCC4 mask register
A76 Reserved
2-8
Name
Serial Communication Controller 3 (Where applicable)
SCC4
MPC860 PowerQUICC UserÕs Manual
Size Section/Page
8 bits 23.20/23-21 (UART)
24.12/24-14 (HDLC)
27.15/27-16 (BISYNC)
29.13/29-13 (Transparent)
8 bytes Ñ
32 bits 22.1.1/22-3
32 bits 22.1.1/22-3
16 bits 22.1.2/22-10
23.16/23-13 (UART)
26.13.3/26-11 (Asynchronous HDLC)
27.11/27-10 (BISYNC)
28.18/28-19 (Ethernet)
29.9/29-8 (Transparent)
2 bytes Ñ
16 bits 22.1.4/22-10
16 bits 22.1.3/22-10
16 bits 23.20/23-21 (UART)
24.12/24-14 (HDLC)
2 bytes
26.13.3/26-11 (Asynchronous HDLC)
16 bits
27.15/27-16 (BISYNC)
29.13/29-13 (Transparent)
1 byte Ñ
8 bits 23.20/23-21 (UART)
24.12/24-14 (HDLC)
27.15/27-16 (BISYNC)
29.13/29-13 (Transparent)
8 bytes Ñ
32 bits 22.1.1/22-3
32 bits 22.1.1/22-3
16 bits 22.1.2/22-10 23.16/23-13 (UART)
26.13.3/26-11 (Asynchronous HDLC)
27.11/27-10 (BiSYNC)
28.18/28-19 (Ethernet)
29.9/29-8 (Transparent)
2 bytes Ñ
16 bits 22.1.4/22-10
16 bits 22.1.3/22-10
16 bits 23.20/23-21 (UART)
24.12/24-14 (HDLC)
2 bytes
26.13.3/26-11 (Asynchronous HDLC)
16 bits
27.15/27-16 (BiSYNC)
29.13/29-13 (Transparent)
1 byte Ñ
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