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Time Point
Fetch
A
B
C
Start fetch handler
D (at least 3
clocks after B)
E
A At time point A the excepting instruction dispatches and begins executing. Previously
dispatched instructions are proceeding through the pipeline.
B The excepting instruction has executed and reached CQ0; previous instructions have
Þnished execution without generating exceptions. The exception is recognized and
between B and D (between 3 and 10 cycles) the effects of any instructions after the one
that generated the interrupt are cancelled and the instructions are ßushed. If the
instruction had not generated an exception, it would have been retired.
C The core fetches the Þrst instructions of the exception handler if the exception handler
is external. It is 5 cycles if it is in the instruction cache and no-show mode is on.
D All state has been restored. During the interval between D and E, the machine is saving
context information in the SRR0 and SRR1 registers, disabling exceptions, placing the
machine in privileged mode, and fetching instructions of the exception handler. The
interval between D and E requires at least one clock. The time between C and E depends
on the memory system and the time it takes to fetch the Þrst instruction of the exception
handler. For full completion queue restore time, it is no less then two clocks.
E The MSR and instruction pointer of the executing process have been saved and control
has been transferred to the exception handler routine. Exception handler instructions
that have been fetched can be dispatched.
7.1.7 Partially Completed Instructions
Partially completed instructions can be reexecuted after the exception is handled. This
precise exception model can simplify exception processing because software does not have
to save the machineÕs internal states, unwind the pipelines, or cleanly terminate the faulting
instruction stream and reverse the process to resume execution of the faulting stream.
MOTOROLA
Table 7-19. Exception Latency
Issue
Faulting instruction issue
First instruction of handler
dispatched
Chapter 7. Exceptions
Part II. PowerPC Microprocessor Module
Instruction Complete
Instruction complete and all
previous instructions complete
Kill Pipeline
Kill pipeline
7-19
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