Table of Contents
Advertisement
CLKOUT
BR
BG
BB
A[0Ð27]
A[28Ð29]
A[30Ð31]
R/W
TSIZ[0Ð1]
BURST
TS
BDIP
Data
TA
BI
Figure 14-18. Burst-Inhibit CycleÐ32-Bit Port Size
14.4.5 Alignment and Data Packing on Transfers
The MPC860 external bus supports only natural address alignment:
¥ Byte access can have any address alignment.
¥ Half-word access must have A[31] = 0b0.
¥ Word access must have A[30Ð31] = 0b00.
¥ For burst accesses A[30Ð31] = 0b00.
Misaligned accesses performed by the CPU are broken into multiple bus accesses with
natural alignment. Misaligned accesses performed by external masters are not supported.
MOTOROLA
n
n+1 Mod 4
00
Chapter 14. MPC860 External Bus Interface
Part IV. Hardware Interface
n+2 Mod 4
n+3 Mod 4
14-23
Advertisement
Table of Contents
