Motorola MPC860 PowerQUICC User Manual page 333

Name Reset
1
D[0Ð31] Hi-Z
DP0 Hi-Z
IRQ3
DP1 Hi-Z
IRQ4
DP2 Hi-Z
IRQ5
DP3
Hi-Z
IRQ6
MOTOROLA
Table 13-1. Signal Descriptions (Continued)
Number Type
See Bidirectional
Figure 13-3 Three-state
V3 Bidirectional
Three-state
V5 Bidirectional
Three-state
W4 Bidirectional
Three-state
V4 Bidirectional
Three-state
Chapter 13. External Signals
Description
Data BusÑBidirectional three-state bus, provides the
general-purpose data path between the MPC860 and all other
devices. The 32-bit data path can be dynamically sized to
support 8-, 16-, or 32-bit transfers. D0 is the msb of the data
bus.
Data Parity 0ÑProvides parity generation and checking for
D[0Ð7] for transfers to a slave device initiated by the MPC860.
The parity function can be deÞned independently for each one
of the addressed memory banks (if controlled by the memory
controller) and for the rest of the slaves sitting on the external
bus. Parity generation and checking is not supported for
external masters.
Interrupt Request 3ÑOne of eight external inputs that can
request (by means of the internal interrupt controller) a service
routine from the core. Note that the interrupt request signal
sent to the interrupt controller is the logical AND of DP0/IRQ3
(if deÞned as IRQ3) and CR/IRQ3 (if deÞned as IRQ3).
Data Parity 1ÑProvides parity generation and checking for
D[8Ð15] for transfers to a slave device initiated by the
MPC860. The parity function can be deÞned independently for
each one of the addressed memory banks (if controlled by the
memory controller) and for the rest of the slaves on the
external bus. Parity generation and checking is not supported
for external masters.
Interrupt Request 4ÑOne of eight external inputs that can
request (by means of the internal interrupt controller) a service
routine from the core. Note that the interrupt request signal
sent to the interrupt controller is the logical AND of this line (if
deÞned as IRQ4) and KR/IRQ4/SPKROUT (if deÞned as
IRQ4).
Data Parity 2ÑProvides parity generation and checking for
D[16Ð23] for transfers to a slave device initiated by the
MPC860. The parity function can be deÞned independently for
each one of the addressed memory banks (if controlled by the
memory controller) and for the rest of the slaves on the
external bus. Parity generation and checking is not supported
for external masters.
Interrupt Request 5ÑOne of eight external inputs that can
request (by means of the internal interrupt controller) a service
routine from the core.
Data Parity 3ÑProvides parity generation and checking for
D[16Ð23] for transfers to a slave device initiated by the
MPC860. The parity function can be deÞned independently for
each one of the addressed memory banks (if controlled by the
memory controller) and for the rest of the slaves on the
external bus. Parity generation and checking is not supported
for external masters.
Interrupt Request 6ÑOne of eight external inputs that can
request (by means of the internal interrupt controller) a service
routine from the core. Note that the interrupt request signal
sent to the interrupt controller is the logical AND of this line (if
deÞned as IRQ6) and the FRZ/IRQ6 (if deÞned as IRQ6).
Part IV. Hardware Interface
13-7